公开(公告)号：US20240339395A1

公开(公告)日：2024-10-10

申请号：US18494183

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungchul KANG ,  Rakhwan KIM ,  Jeongik KIM ,  Chunghwan SHIN ,  Daeun KIM ,  Seongdong LIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76876 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092

Abstract: A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a gate contact structure electrically connected to the outer electrode. The gate contact structure may include a lower gate contact on a top surface of the outer electrode and an upper gate contact on the lower gate contact. The lower gate contact may include a first liner pattern, a first filling pattern on the first liner pattern, and a nucleation pattern between the first liner pattern and the first filling pattern. The upper gate contact may not include the nucleation pattern.