公开(公告)号：US20180358345A1

公开(公告)日：2018-12-13

申请号：US15787244

申请日：2017-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUBO QIAN ,  Byung-Sung KIM ,  CHUL-HONG PARK ,  Haewang LEE

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L21/8238 ,  H01L27/092 ,  H03K19/0948 ,  H01L23/535

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2027/11875 ,  H03K19/0948

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes first and second logic cells adjacent to each other in a first direction on a substrate, a gate electrode extending in the first direction in each of the first and second logic cells, a power line extending in a second direction at a boundary between the first and second logic cells, and a connection structure electrically connecting the power line to an active pattern of the first logic cell and to an active pattern of the second logic cell. The connection structure lies below the power line and extends from the first logic cell to the second logic cell. A top surface of the connection structure is at a higher level than that of a top surface of the gate electrode.

公开(公告)号：US20190286785A1

公开(公告)日：2019-09-19

申请号：US16432139

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  Chulhong PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L27/02

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.

公开(公告)号：US20180129773A1

公开(公告)日：2018-05-10

申请号：US15610751

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  CHULHONG PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L21/8234 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/823437 ,  H01L27/0207

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.

公开(公告)号：US20150061161A1

公开(公告)日：2015-03-05

申请号：US14467597

申请日：2014-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-kyung LEE ,  Byoung-lyong CHOI ,  Won-Jae JOO ,  Byung-Sung KIM ,  Jae-Hyun LEE ,  Jong-Woon LEE ,  Dong-Mok WHANG

IPC: H01L23/00 ,  H01B5/00 ,  H01B1/04

CPC classification number: H01L24/45 ,  H01B1/04 ,  H01L24/43 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45186 ,  H01L2224/45193 ,  H01L2224/45663 ,  H01L2224/45693 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/00 ,  H01L2924/01006 ,  H01L2924/00014

Abstract: According to example embodiments, a wire structure includes a first wire that includes a first wire core and a first carbon shell surrounding the first wire core, and a second wire that extends in a longitudinal direction from the first wire. The first wire core has a wire shape. The first carbon shell contains carbon.

Abstract translation: 根据示例性实施例，线结构包括第一线，其包括第一线芯和围绕第一线芯的第一碳壳，以及沿着纵向方向从第一线延伸的第二线。 第一线芯具有线形。 第一个碳壳含有碳。