公开(公告)号：US20230361150A1

公开(公告)日：2023-11-09

申请号：US18130014

申请日：2023-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeyeon Park ,  Boseong Kim ,  Yunki Lee

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14607

Abstract: A manufacturing method of an image sensor includes, operations of: forming a color filter layer over a plurality of pixel regions having a plurality of photodetectors and arranged in a matrix on a substrate, and patterning the color filter layer with a mask including patterns disposed adjacently in a diagonal direction of the matrix, to form color filters for some of the plurality of pixel regions on the substrate. Each of the patterns may include a rectangular main pattern and sub-patterns outwardly extending from corners of the main patterns. Sizes of sub-patterns of different adjacent patterns that face each other may have sizes that are smaller than other sub-patterns of the adjacent patterns.

公开(公告)号：US11791321B2

公开(公告)日：2023-10-17

申请号：US17580047

申请日：2022-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Young Lee ,  Dongok Kwak ,  Boseong Kim ,  Sang Sub Song ,  Joonyoung Oh

IPC: H01L23/538 ,  H01L25/10 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/3025

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

公开(公告)号：US11251169B2

公开(公告)日：2022-02-15

申请号：US16549917

申请日：2019-08-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Young Lee ,  Dongok Kwak ,  Boseong Kim ,  Sang Sub Song ,  Joonyoung Oh

IPC: H01L23/31 ,  H01L25/10 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

公开(公告)号：US10109617B2

公开(公告)日：2018-10-23

申请号：US15652559

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Ryul Lee ,  Boseong Kim ,  Taeduk Nam ,  Wangju Lee

IPC: H01L23/552 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

Abstract: A solid state drive package is provided. The solid state drive package may include an integrated circuit substrate including: a lower redistribution layer; a first chip and a second chip provided on the lower redistribution layer; and a connection substrate provided on the lower redistribution layer, the connection substrate provided on an outer periphery of the first chip and the second chip; and a plurality of third chips provided on the integrated circuit substrate. The plurality of third chips are electrically connected to the first chip and the second chip via the connection substrate and the lower redistribution layer.