公开(公告)号：US20140269032A1

公开(公告)日：2014-09-18

申请号：US13851274

申请日：2013-03-27

Applicant: Samsung Electronics Co., LTD.

Inventor： Adrian E. Ong ,  Alexey Vasilyevitch Khvalkovskiy ,  Dmytro Apalkov

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18

Abstract: A magnetic memory includes memory array tiles (MATs), intermediate circuitry, global bit lines and global circuitry. Each MAT includes bit lines, word lines, and magnetic storage cells having magnetic junction(s), selection device(s) and at least part of a spin-orbit interaction (SO) active layer adjacent to the magnetic junction(s). The SO active layer exerts a SO torque on the magnetic junction(s) due to a preconditioning current passing through the SO active layer. The magnetic junction(s) are programmable using write current(s) driven through the magnetic junction(s) and the preconditioning current. The bit and word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a portion of the MATs. The global circuitry selects and drives portions of the global bit lines for read operations and write operations.

Abstract translation: 磁存储器包括存储器阵列瓦片（MATs），中间电路，全局位线和全局电路。 每个MAT包括具有磁结，选择装置的位线，字线和磁存储单元以及与磁结相邻的自旋轨道相互作用（SO）有源层的至少一部分。 SO活性层由于预处理电流通过SO活性层而在磁结上施加SO转矩。 磁结可以使用通过磁结驱动的写入电流和预调节电流进行编程。 位和字线对应于磁存储单元。 中间电路控制MAT内的读写操作。 每个全局位线对应于MAT的一部分。 全局电路选择并驱动部分全局位线进行读操作和写操作。

公开(公告)号：US09111625B2

公开(公告)日：2015-08-18

申请号：US14091319

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Adrian E. Ong

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1697 ,  G11C29/021 ,  G11C29/028

Abstract: An adaptive dual voltage memory write driver system can include an adaptive write voltage generator circuit to provide a first adjustable write voltage and to provide a second adjustable write voltage. The adaptive dual voltage memory write driver system can include an array of dummy memory cells coupled to the adaptive write voltage generator circuit and configured to provide resistive path tracking information to the adaptive write voltage generator circuit. The adjustable write voltages can be automatically increased or decreased responsive to the resistive path tracking information. A tri-state write driver circuit can provide a first adjustable write voltage source for writing “0”s and a second adjustable write voltage source for writing “1”s. A method for generating adjustable memory write voltages using dummy resistive path tracking may include receiving resistive path tracking information from a dummy section, and generating adjustable write voltages based on the resistive path tracking information.

Abstract translation: 自适应双电压存储器写入驱动器系统可以包括自适应写入电压发生器电路，以提供第一可调写入电压并提供第二可调写入电压。 自适应双电压存储器写入驱动器系统可以包括耦合到自适应写入电压发生器电路的虚拟存储器单元的阵列，并且被配置为向自适应写入电压发生器电路提供电阻路径跟踪信息。 响应于电阻路径跟踪信息可以自动地增加或减小可调写入电压。 三态写驱动器电路可以提供用于写“0”的第一可调写电压源和用于写“1”的第二可调写电压源。 使用虚拟电阻路径跟踪产生可调节存储器写入电压的方法可以包括从虚拟部分接收电阻路径跟踪信息，以及基于电阻路径跟踪信息产生可调写入电压。

公开(公告)号：US09076541B2

公开(公告)日：2015-07-07

申请号：US13851274

申请日：2013-03-27

Applicant: Samsung Electronics Co., LTD.

Inventor： Adrian E. Ong ,  Alexey Vasilyevitch Khvalkovskiy ,  Dmytro Apalkov

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18

Abstract: A magnetic memory includes memory array tiles (MATs), intermediate circuitry, global bit lines and global circuitry. Each MAT includes bit lines, word lines, and magnetic storage cells having magnetic junction(s), selection device(s) and at least part of a spin-orbit interaction (SO) active layer adjacent to the magnetic junction(s). The SO active layer exerts a SO torque on the magnetic junction(s) due to a preconditioning current passing through the SO active layer. The magnetic junction(s) are programmable using write current(s) driven through the magnetic junction(s) and the preconditioning current. The bit and word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a portion of the MATs. The global circuitry selects and drivesportions of the global bit lines for read operations and write operations.

Abstract translation: 磁存储器包括存储器阵列瓦片（MATs），中间电路，全局位线和全局电路。 每个MAT包括具有磁结，选择装置的位线，字线和磁存储单元以及与磁结相邻的自旋轨道相互作用（SO）有源层的至少一部分。 SO活性层由于预处理电流通过SO活性层而在磁结上施加SO转矩。 磁结可以使用通过磁结驱动的写入电流和预调节电流进行编程。 位和字线对应于磁存储单元。 中间电路控制MAT内的读写操作。 每个全局位线对应于MAT的一部分。 全局电路选择和驱动全局位线的部分，用于读操作和写操作。