公开(公告)号：US20140027759A1

公开(公告)日：2014-01-30

申请号：US13733820

申请日：2013-01-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Kyoung Won LEE ,  Gun Hee KIM ,  Young Joo CHOI

IPC: H01L33/44

CPC classification number: H01L33/44 ,  H01L27/1225 ,  H01L29/7869

Abstract: A display device according to an exemplary embodiment of the present invention includes a semiconductor layer; a data line disposed on the semiconductor layer, and a source electrode as well as a drain electrode disposed on the semiconductor layer and facing the source electrode. The semiconductor layer is made of an oxide semiconductor including indium, tin, and zinc. An atomic percent of indium in the oxide semiconductor is equal to or larger than about 10 at % and equal to or smaller than about 90 at %, an atomic percent of zinc in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 60 at %, and an atomic percent of tin in the oxide semiconductor is equal to or larger than about 5 at % and equal to or smaller than about 45 at %, and the data line and the drain electrode comprise copper.

Abstract translation: 根据本发明的示例性实施例的显示装置包括半导体层; 设置在半导体层上的数据线，以及设置在半导体层上并面向源电极的源电极以及漏电极。 半导体层由包括铟，锡和锌的氧化物半导体制成。 氧化物半导体中的铟的原子百分比等于或大于约10原子％且等于或小于约90原子％，氧化物半导体中的锌的原子百分比等于或大于约5原子％，以及 等于或小于约60at％，并且氧化物半导体中的锡的原子百分比等于或大于约5at％且等于或小于约45at％，并且数据线和漏电极包括 铜。

公开(公告)号：US20130306972A1

公开(公告)日：2013-11-21

申请号：US13725333

申请日：2012-12-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young RYU ,  Ki Won KIM ,  Jae Woo PARK ,  Kap Soo YOON ,  Young Joo CHOI

IPC: H01L29/786 ,  H01L33/08

CPC classification number: H01L29/786 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/08

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于基板上的栅极线; 位于栅极线上的栅极绝缘层; 位于所述栅极绝缘层上且具有沟道部分的半导体层; 包括源电极和漏电极的数据线，所述源极和漏极都位于所述半导体层上; 位于数据线和漏电极上并具有形成在其中的接触孔的钝化层; 位于所述钝化层上的像素电极，其中所述像素电极在所述接触孔内接触所述漏电极，并且所述半导体层的沟道部分和所述接触孔在所述衬底的平面图中与所述栅极线重叠。

公开(公告)号：US20150187813A1

公开(公告)日：2015-07-02

申请号：US14659120

申请日：2015-03-16

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。

公开(公告)号：US20160216586A1

公开(公告)日：2016-07-28

申请号：US14956472

申请日：2015-12-02

Applicant: Samsung Display Co., Ltd.

Inventor： Young Joo CHOI ,  Chang Ha KWAK ,  Hee Jung YOON ,  Jin Yool KIM ,  Jae Phil LEE

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F2001/134372 ,  G02F2202/10

Abstract: A liquid crystal display and a manufacturing method thereof include a planar-shaped common electrode disposed directly on a common voltage line, and a semiconductor layer disposed on the common electrode and a gate line, serving as a gate insulating layer. Accordingly, it is possible to prevent signal delay of the common voltage and lower the manufacturing cost by disposing a common electrode and a pixel electrode on one substrate and disposing a common electrode directly on a common voltage line.

Abstract translation: 液晶显示器及其制造方法包括直接设置在公共电压线上的平面状公共电极和配置在公共电极上的半导体层和用作栅极绝缘层的栅极线。 因此，可以通过在一个基板上设置公共电极和像素电极并将公共电极直接设置在公共电压线上来防止公共电压的信号延迟并降低制造成本。

公开(公告)号：US20160197103A1

公开(公告)日：2016-07-07

申请号：US14739295

申请日：2015-06-15

Applicant: Samsung Display Co., Ltd.

Inventor： Young Joo CHOI

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  H01L27/1225

Abstract: A thin-film transistor (TFT) substrate including a first region including a semiconductor layer, a first etch barrier layer covering the semiconductor layer, a first contact hole and a second contact hole, which are formed through the first etch barrier layer, a source electrode, which is disposed on the first etch barrier layer and is electrically connected to the semiconductor layer via the first contact hole, a drain electrode, which is disposed on the first etch barrier layer to be isolated from the source electrode, is electrically connected to the semiconductor layer via the second contact hole and has a transparent conductive oxide layer and a metal layer, and a pixel electrode, which is disposed on the first etch barrier layer and includes the transparent conductive oxide layer.

Abstract translation: 一种薄膜晶体管（TFT）基板，包括通过第一蚀刻阻挡层形成的包括半导体层，覆盖半导体层的第一蚀刻阻挡层，第一接触孔和第二接触孔的第一区域，源极 电极，其设置在第一蚀刻阻挡层上并且经由第一接触孔电连接到半导体层，设置在与源电极隔离的第一蚀刻阻挡层上的漏极电连接到 所述半导体层经由所述第二接触孔并具有透明导电氧化物层和金属层，以及像素电极，其设置在所述第一蚀刻阻挡层上并且包括所述透明导电氧化物层。

公开(公告)号：US20150206976A1

公开(公告)日：2015-07-23

申请号：US14283063

申请日：2014-05-20

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Won SONG ,  Young Joo CHOI

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode and the substrate, an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode, a source electrode disposed on a part of the oxide semiconductor pattern, and a drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode, wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region other than the channel region.

Abstract translation: 薄膜晶体管包括设置在基板上的栅极电极，设置在栅极电极和基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体图案，其中氧化物半导体的一部分与栅电极重叠， 设置在所述氧化物半导体图案的一部分上的源极，以及设置在与所述源极间隔开的所述氧化物半导体图案的一部分上的漏电极，其中，所述沟道区中的所述栅极绝缘层的厚度与 栅电极比剩余区域中的栅极绝缘层的厚度薄，除了沟道区域之外的剩余区域。

公开(公告)号：US20150144939A1

公开(公告)日：2015-05-28

申请号：US14291535

申请日：2014-05-30

Applicant: Samsung Display Co., Ltd.

Inventor： Young Joo CHOI ,  Joon Geol KIM ,  Seung-Ho JUNG ,  Kang Moon JO

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618

Abstract: A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，包括栅电极; 栅极线上的第一栅极绝缘层; 在所述第一栅极绝缘层上的半导体层，并且与所述栅电极重叠; 在所述半导体层和所述第一栅极绝缘层上的第二栅极绝缘层和所述第二栅极绝缘层中的所述半导体层暴露的开口; 第二栅绝缘层和半导体层上的漏极和源极彼此面对; 第一场产生电极; 以及连接到漏电极的第二场产生电极。 半导体层包括氧化物半导体层，以及氧化物半导体层上的第一和第二辅助层，并且彼此分离。 漏极和源电极的边缘分别设置在第一和第二辅助层的边缘的内侧。

公开(公告)号：US20160216584A1

公开(公告)日：2016-07-28

申请号：US14805237

申请日：2015-07-21

Applicant: Samsung Display Co., Ltd.

Inventor： Keum Hee LEE ,  Young Joo CHOI

IPC: G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/1368

CPC classification number: G02F1/136286 ,  G02F1/13439 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/4908

Abstract: A liquid crystal display and a manufacturing method thereof are disclosed, whereby a common electrode having a planar shape is formed directly on a common voltage line, and a semiconductor layer is formed on the common electrode and a gate line. The common electrode and a pixel electrode are formed on one substrate, with the common electrode being formed directly on the common voltage line. Accordingly, the costs of manufacturing the liquid crystal display may be reduced, and signal delay of a common voltage can be prevented.

Abstract translation: 公开了一种液晶显示器及其制造方法，由此在公共电压线上直接形成具有平面形状的公共电极，并且在公共电极和栅极线上形成半导体层。 公共电极和像素电极形成在一个基板上，公共电极直接形成在公共电压线上。 因此，可以降低制造液晶显示器的成本，并且可以防止公共电压的信号延迟。

公开(公告)号：US20150311234A1

公开(公告)日：2015-10-29

申请号：US14795431

申请日：2015-07-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo PARK ,  Do-Hyun KIM ,  Young Joo CHOI ,  Dong Hoon LEE ,  Sung Haeng CHO

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，设置在基板上并且包括栅电极，包括设置在基板上的氧化物半导体的半导体层以及设置在基板上的数据线层，并且包括与栅极交叉的数据线 线，连接到数据线的源电极和面对源电极的漏电极。 此外，数据线层的数据线，源电极或漏电极中的至少一个包括阻挡层和设置在阻挡层上的主配线层。 主配线层包括铜或铜合金。 此外，阻挡层包括金属氧化物，并且金属氧化物包括锌。

公开(公告)号：US20140332889A1

公开(公告)日：2014-11-13

申请号：US14012580

申请日：2013-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。