公开(公告)号：US20150206976A1

公开(公告)日：2015-07-23

申请号：US14283063

申请日：2014-05-20

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Won SONG ,  Young Joo CHOI

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A thin film transistor includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode and the substrate, an oxide semiconductor pattern disposed on the gate insulating layer, wherein a part of the oxide semiconductor overlaps the gate electrode, a source electrode disposed on a part of the oxide semiconductor pattern, and a drain electrode disposed on a part of the oxide semiconductor pattern spaced apart from the source electrode, wherein a thickness of the gate insulating layer in a channel region, the channel region overlapping the gate electrode, is thinner than a thickness of the gate insulating layer in a remaining region, the remaining region other than the channel region.

Abstract translation: 薄膜晶体管包括设置在基板上的栅极电极，设置在栅极电极和基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体图案，其中氧化物半导体的一部分与栅电极重叠， 设置在所述氧化物半导体图案的一部分上的源极，以及设置在与所述源极间隔开的所述氧化物半导体图案的一部分上的漏电极，其中，所述沟道区中的所述栅极绝缘层的厚度与 栅电极比剩余区域中的栅极绝缘层的厚度薄，除了沟道区域之外的剩余区域。

公开(公告)号：US20150200212A1

公开(公告)日：2015-07-16

申请号：US14466317

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu XUN ,  Jae Woo PARK ,  Jae Won SONG ,  Keum Hee LEE ,  June Whan CHOI

IPC: H01L27/12 ,  H01L21/443 ,  H01L21/4763 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/443 ,  H01L21/76852 ,  H01L23/53238 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

Abstract translation: 如下提供薄膜晶体管阵列面板。 栅电极设置在基板上。 半导体层设置在栅电极上。 栅极绝缘层设置在栅电极和半导体层之间。 源电极设置在半导体层的第一侧上，具有第一侧表面。 漏电极设置在半导体层的第二侧上，具有第二侧表面。 第一和第二侧表面限定了与栅电极重叠的间隔。 金属硅化物层设置在第一和第二侧表面上。 在金属硅化物层，源电极和漏电极上设置钝化层。 钝化层不与第一和第二侧表面接触。