公开(公告)号：US20150144939A1

公开(公告)日：2015-05-28

申请号：US14291535

申请日：2014-05-30

Applicant: Samsung Display Co., Ltd.

Inventor： Young Joo CHOI ,  Joon Geol KIM ,  Seung-Ho JUNG ,  Kang Moon JO

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618

Abstract: A thin film transistor array panel includes: a gate line including a gate electrode; a first gate insulating layer on the gate line; a semiconductor layer on the first gate insulating layer and overlapping the gate electrode; a second gate insulating layer on the semiconductor layer and the first gate insulating layer, and an opening in the second gate insulating layer and through which the semiconductor layer is exposed; drain and source electrodes on the second gate insulating and semiconductor layers and facing each other; a first field generating electrode; and a second field generating electrode connected to the drain electrode. The semiconductor layer includes an oxide semiconductor layer, and first and second auxiliary layers on the oxide semiconductor layer and separated from each other. An edge of the drain and source electrodes is disposed inside an edge of the first and second auxiliary layers, respectively.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，包括栅电极; 栅极线上的第一栅极绝缘层; 在所述第一栅极绝缘层上的半导体层，并且与所述栅电极重叠; 在所述半导体层和所述第一栅极绝缘层上的第二栅极绝缘层和所述第二栅极绝缘层中的所述半导体层暴露的开口; 第二栅绝缘层和半导体层上的漏极和源极彼此面对; 第一场产生电极; 以及连接到漏电极的第二场产生电极。 半导体层包括氧化物半导体层，以及氧化物半导体层上的第一和第二辅助层，并且彼此分离。 漏极和源电极的边缘分别设置在第一和第二辅助层的边缘的内侧。

公开(公告)号：US20170038427A1

公开(公告)日：2017-02-09

申请号：US15017742

申请日：2016-02-08

Applicant: Samsung Display Co. Ltd.

Inventor： Joon Geol KIM ,  Si Joon KIM ,  Hee Seon KIM

IPC: G01R31/26 ,  H01L27/32

CPC classification number: H01L27/3244 ,  G09G3/006 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2330/10

Abstract: An array test apparatus includes a signal transmission unit which transmits a data signal to each of a plurality of data lines of a low-temperature polysilicon (“LTPS”) substrate, a signal measurement unit which measures the data signal of each of the data lines of the LTPS substrate, a timer which generates a horizontal period for setting a section in which the data signal is transmitted from the signal transmission unit to each of the data lines and a section in which the data signal output from each of the data lines is measured by the signal measurement unit, and a determination unit which determines whether each of the data lines of the LTPS substrate is normal based on the data signal measured by the signal measurement unit.

Abstract translation: 阵列测试装置包括：将数据信号发送到低温多晶硅（“LTPS”）基板的多条数据线中的每条数据线的信号传输单元，测量每条数据线的数据信号的信号测量单元 的定时器，产生用于设置数据信号从信号发送单元发送到每条数据线的部分的水平周期的定时器以及从每个数据线输出的数据信号的部分是 由信号测量单元测量的确定单元，以及确定单元，其基于由信号测量单元测量的数据信号来确定LTPS基板的每条数据线是否正常。

公开(公告)号：US20140332889A1

公开(公告)日：2014-11-13

申请号：US14012580

申请日：2013-08-28

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。

公开(公告)号：US20220140059A1

公开(公告)日：2022-05-05

申请号：US17475950

申请日：2021-09-15

Applicant: Samsung Display Co., LTD.

Inventor： Jong In KIM ,  Hyun Seong KANG ,  Joon Geol KIM ,  Seung Sok SON ,  Woo Geun LEE ,  Young Jae JEON ,  Soo Jung CHAE ,  Ji Yun HONG

IPC: H01L27/32 ,  H01L51/00

Abstract: A display device includes a pixel electrode disposed on a first surface of a substrate, a light emitting layer disposed on the pixel electrode, a common electrode disposed on the light emitting layer, a supply voltage line disposed on the first surface of the substrate and applying a voltage to the common electrode, a first auxiliary conductive layer disposed on a second surface of the substrate, and a first connection conductive layer at least partially disposed on a side surface of the substrate and electrically connecting the first auxiliary conductive layer to the supply voltage line.

公开(公告)号：US20150187813A1

公开(公告)日：2015-07-02

申请号：US14659120

申请日：2015-03-16

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho JUNG ,  Young Joo CHOI ,  Joon Geol KIM ,  Kang Moon JO ,  Sho Yeon KIM ,  Byung Hwan CHU ,  Woo Geun LEE ,  Woo-Seok JEON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L27/1288

Abstract: A thin film transistor array panel is disclosed. The thin film transistor array panel may include a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, a data wiring layer disposed on the substrate and including a data line crossing the gate line, a source electrode connected to the data line and a drain electrode facing the source electrode, a polymer layer covering the source electrode and the drain electrode, and a passivation layer disposed on the polymer layer. The data wiring layer may include copper or a copper alloy and the polymer layer may include fluorocarbon.

Abstract translation: 公开了薄膜晶体管阵列面板。 薄膜晶体管阵列面板可以包括设置在基板上并包括栅电极的栅极线，包括设置在基板上的氧化物半导体的半导体层，设置在基板上的数据布线层，并且包括与栅极线交叉的数据线 连接到数据线的源电极和面对源电极的漏电极，覆盖源电极和漏电极的聚合物层和设置在聚合物层上的钝化层。 数据布线层可以包括铜或铜合金，并且聚合物层可以包括碳氟化合物。