公开(公告)号：US20170077246A1

公开(公告)日：2017-03-16

申请号：US15343234

申请日：2016-11-04

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/4757 ,  H01L21/465 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20170040349A1

公开(公告)日：2017-02-09

申请号：US15332079

申请日：2016-10-24

Applicant: Samsung Display Co., Ltd.

Inventor： Je-Hun LEE ,  Ki-Won KIM ,  Do-Hyun KIM ,  Woo-Geun LEE ,  Kap-Soo YOON

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

公开(公告)号：US20140312344A1

公开(公告)日：2014-10-23

申请号：US14319012

申请日：2014-06-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je-Hun LEE ,  Ki-Won KIM ,  Do-Hyun KIM ,  Woo-Geun LEE ,  Kap-Soo YOON

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

公开(公告)号：US20140147947A1

公开(公告)日：2014-05-29

申请号：US14168971

申请日：2014-01-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yu-Gwang JEONG ,  Young-Wook LEE ,  Sang-Gab KIM ,  Woo-Geun LEE ,  Min-Seok OH ,  Jang-Soo KIM ,  Kap-Soo YOON ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Seung-Hwan SHIM ,  Sung-Hoon YANG ,  Ki-Hun JEONG

IPC: H01L27/12

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US20150318317A1

公开(公告)日：2015-11-05

申请号：US14798123

申请日：2015-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/441 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20160020331A1

公开(公告)日：2016-01-21

申请号：US14858281

申请日：2015-09-18

Applicant: Samsung Display Co., Ltd.

Inventor： Ki-Won KIM ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Hyun-Jung LEE

IPC: H01L29/786 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/66765 ,  H01L29/78633

Abstract: A display substrate is provided. The display substrate includes a gate interconnection disposed on an insulating substrate, an oxide semiconductor pattern disposed on the gate interconnection and including an oxide semiconductor, and a data interconnection disposed on the oxide semiconductor pattern to interconnect the gate interconnection. The oxide semiconductor pattern includes a first oxide semiconductor pattern having a first oxide and a first element and a second oxide semiconductor pattern having a second oxide.

Abstract translation: 提供显示基板。 显示基板包括布置在绝缘基板上的栅极互连，设置在栅极互连上并包括氧化物半导体的氧化物半导体图案，以及布置在氧化物半导体图案上以互连栅极互连的数据互连。 氧化物半导体图案包括具有第一氧化物和第一元素的第一氧化物半导体图案以及具有第二氧化物的第二氧化物半导体图案。

公开(公告)号：US20150340507A1

公开(公告)日：2015-11-26

申请号：US14809372

申请日：2015-07-27

Applicant: Samsung Display Co., Ltd.

Inventor： Je-Hun LEE ,  Ki-Won KIM ,  Do-Hyun KIM ,  Woo-Geun LEE ,  Kap-Soo YOON

IPC: H01L29/786 ,  H01L23/532 ,  H01L29/45 ,  H01L29/51 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

公开(公告)号：US20140209903A1

公开(公告)日：2014-07-31

申请号：US14230787

申请日：2014-03-31

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。