公开(公告)号：US20170077144A1

公开(公告)日：2017-03-16

申请号：US15342756

申请日：2016-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.

Abstract translation: 一种基板，包括栅极布线和设置在基板上的栅极电极的栅极布线，设置在与栅极布线相同的层上的存储线，设置在栅极布线和存储线上的栅极绝缘层，设置的氧化物半导体层图案 在栅极绝缘层上，包括与栅极线交叉的数据线的数据布线，设置在氧化物半导体层图案的一侧上的源电极和设置在氧化物半导体层的另一侧上的漏极，以及包括 设置在所述存储线和所述数据线之间并且部分地重叠所述数据线和所述存储线的第一蚀刻停止部。

公开(公告)号：US20150318317A1

公开(公告)日：2015-11-05

申请号：US14798123

申请日：2015-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/441 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20130248866A1

公开(公告)日：2013-09-26

申请号：US13897879

申请日：2013-05-20

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L29/786

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract translation: 提供薄膜晶体管（TFT）阵列基板及其制造方法。 TFT阵列基板可以包括设置在基板上的栅极线，包括栅极线和栅电极，设置在栅电极上的氧化物半导体层图案，设置在氧化物半导体层图案上的数据线，并且包括源电极和 薄膜晶体管（TFT）的漏电极和栅电极以及沿着与栅极线交叉的方向延伸的数据线，以及蚀刻停止图案，设置在源极/漏极之间形成TFT的区域，以及 氧化物半导体层图案和栅极线与数据线在栅极线与数据线之间重叠的区域。

公开(公告)号：US20210143187A1

公开(公告)日：2021-05-13

申请号：US17124497

申请日：2020-12-17

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20150029426A1

公开(公告)日：2015-01-29

申请号：US14512354

申请日：2014-10-10

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Wook LEE ,  Hwa-Yeul OH ,  Pil-Sang YUN ,  Je-Hyeong PARK

IPC: G02F1/133

CPC classification number: G02F1/13306 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345 ,  G09G3/3659 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0809 ,  G09G2300/0876 ,  G09G2320/028

Abstract: The present invention relates to a liquid crystal display and a driving method thereof. The liquid crystal display of the present invention includes a pixel electrode including: a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other; a first thin film transistor connected to the first subpixel electrode; a second thin film transistor connected to the second subpixel electrode; a third thin film transistor connected to the third subpixel electrode; a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode; a first gate line connected to the first to third thin film transistors; a second gate line connected to the fourth thin film transistor; a data line connected to the first and second thin film transistors; and a storage electrode line connected to the third thin film transistor.

Abstract translation: 本发明涉及一种液晶显示器及其驱动方法。 本发明的液晶显示装置具有：像素电极，具有：第一子像素电极，第二子像素电极以及与之分离的第三子像素电极; 连接到第一子像素电极的第一薄膜晶体管; 连接到第二子像素电极的第二薄膜晶体管; 连接到第三子像素电极的第三薄膜晶体管; 连接到第二子像素电极和第三子像素电极的第四薄膜晶体管; 连接到第一至第三薄膜晶体管的第一栅极线; 连接到第四薄膜晶体管的第二栅极线; 连接到第一和第二薄膜晶体管的数据线; 以及与第三薄膜晶体管连接的存储电极线。

公开(公告)号：US20140209903A1

公开(公告)日：2014-07-31

申请号：US14230787

申请日：2014-03-31

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20130149814A1

公开(公告)日：2013-06-13

申请号：US13758716

申请日：2013-02-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Wook LEE ,  Hong-Suk YOO ,  Jean-Ho SONG ,  Jae-Hyoung YOUN ,  Woo-Geun LEE ,  Ki-Won KIM ,  Jong-In KIM

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US20220384491A1

公开(公告)日：2022-12-01

申请号：US17886489

申请日：2022-08-12

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

公开(公告)号：US20170077246A1

公开(公告)日：2017-03-16

申请号：US15343234

申请日：2016-11-04

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/4757 ,  H01L21/465 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20160284734A1

公开(公告)日：2016-09-29

申请号：US14984448

申请日：2015-12-30

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun LEE ,  Katsumi ABE ,  Young-Wook LEE

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/786 ,  H01L21/56 ,  H01L29/24 ,  H01L23/31

CPC classification number: H01L27/124 ,  G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0214 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3171 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

Abstract translation: 薄膜晶体管阵列面板包括衬底，设置在衬底上的第一栅极电极，设置在衬底上的电压线，设置在第一栅电极和电压线上的栅极绝缘层，包括氧化物半导体材料的半导体图案 设置在所述栅极绝缘层上，在所述半导体图案上彼此间隔设置的源电极和漏电极，设置在所述源电极和所述漏电极上的第一钝化层，以及设置在所述第一钝化层上的第一电极 并与电压线连接。