公开(公告)号：US20170077246A1

公开(公告)日：2017-03-16

申请号：US15343234

申请日：2016-11-04

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L29/417 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/4757 ,  H01L21/465 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20150318317A1

公开(公告)日：2015-11-05

申请号：US14798123

申请日：2015-07-13

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/441 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20150270296A1

公开(公告)日：2015-09-24

申请号：US14727286

申请日：2015-06-01

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang-Ho LEE ,  Jang-Soo KIM ,  Hong-Suk YOO ,  Sang-Soo KIM ,  Shi-Yul KIM ,  Jae-Hyoung YOUN

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

Abstract translation: 薄膜晶体管（“TFT”）阵列面板包括： 绝缘基板，设置在所述绝缘基板上并包括漏电极的TFT，覆盖所述TFT的钝化层，并且包括设置在其中的所述漏电极对应的接触部分，所述隔板包括设置在所述钝化层上的有机材料，并且包括 横向部分，纵向部分和设置在漏电极上的接触部分，设置在钝化层上并设置在由隔板限定的区域中的滤色器，设置在隔板上的有机覆盖层和滤色器，以及 设置在所述有机覆盖层上的像素电极，并且通过所述钝化层的接触部分和所述隔离物的接触部分连接到所述漏电极，其中在所述有机覆盖层中形成接触孔，所述接触孔对应于所述钝化层的接触部分 钝化层。

公开(公告)号：US20150129885A1

公开(公告)日：2015-05-14

申请号：US14605749

申请日：2015-01-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Byeong-Beom KIM ,  Je-Hyeong PARK ,  Jae-Hyoung YOUN ,  Jean-Ho SONG ,  Jong-In KIM

IPC: H01L27/12 ,  H01L23/482

CPC classification number: H01L27/124 ,  C23C14/14 ,  C23C14/34 ,  H01L23/4827 ,  H01L23/52 ,  H01L29/786 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.

Abstract translation: 根据本发明的示例性实施方案的薄膜的形成方法包括以大约1.5至大约3W / cm 2的功率密度和处于该范围内的惰性气体的压力形成薄膜 大约0.2至大约0.3Pa。这个过程产生一个非晶金属薄膜阻挡层，防止相邻层的不期望的扩散，即使该阻挡层比许多传统的阻挡层薄。

公开(公告)号：US20160181283A1

公开(公告)日：2016-06-23

申请号：US15041746

申请日：2016-02-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang-Ho LEE ,  Jang-Soo KIM ,  Hong-Suk YOO ,  Sang-Soo KIM ,  Shi-Yul KIM ,  Jae-Hyoung YOUN

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136222 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor (“TFT”) array panel includes; an insulation substrate, a TFT disposed on the insulation substrate and including a drain electrode, a passivation layer covering the TFT and including a contact portion disposed therein corresponding to the drain electrode, a partition comprising an organic material disposed on the passivation layer, and including a transverse portion, a longitudinal portion, and a contact portion disposed on the drain electrode, a color filter disposed on the passivation layer and disposed in a region defined by the partition, an organic capping layer disposed on the partition and the color filter, and a pixel electrode disposed on the organic capping layer, and connected to the drain electrode through the contact portion of the passivation layer and the contact portion of the partition, wherein a contact hole is formed in the organic capping layer corresponding to the contact portion of the passivation layer.

公开(公告)号：US20140209903A1

公开(公告)日：2014-07-31

申请号：US14230787

申请日：2014-03-31

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Ki-Won KIM ,  Hye-Young RYU ,  Woo-Geun LEE ,  Seung-Ha CHOI ,  Jae-Hyoung YOUN ,  Kyoung-Jae CHUNG ,  Young-Wook LEE ,  Je-Hun LEE ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Dong-Ju YANG ,  Young-Joo CHOI

IPC: H01L27/12

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract translation: 薄膜晶体管面板包括绝缘基板，设置在绝缘基板上的栅极绝缘层，设置在栅极绝缘层上的氧化物半导体层，设置在氧化物半导体层上的蚀刻停止器，以及设置在源极电极和漏极上的 在蚀刻停止器上。

公开(公告)号：US20130149814A1

公开(公告)日：2013-06-13

申请号：US13758716

申请日：2013-02-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Wook LEE ,  Hong-Suk YOO ,  Jean-Ho SONG ,  Jae-Hyoung YOUN ,  Woo-Geun LEE ,  Ki-Won KIM ,  Jong-In KIM

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。