公开(公告)号：US20150311234A1

公开(公告)日：2015-10-29

申请号：US14795431

申请日：2015-07-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo PARK ,  Do-Hyun KIM ,  Young Joo CHOI ,  Dong Hoon LEE ,  Sung Haeng CHO

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，设置在基板上并且包括栅电极，包括设置在基板上的氧化物半导体的半导体层以及设置在基板上的数据线层，并且包括与栅极交叉的数据线 线，连接到数据线的源电极和面对源电极的漏电极。 此外，数据线层的数据线，源电极或漏电极中的至少一个包括阻挡层和设置在阻挡层上的主配线层。 主配线层包括铜或铜合金。 此外，阻挡层包括金属氧化物，并且金属氧化物包括锌。

公开(公告)号：US20150049276A1

公开(公告)日：2015-02-19

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young CHOI ,  Bo Sung KIM ,  Jae Woo PARK ,  Hee Jun BYEON ,  Young-Wook LEE ,  Moon-Keun CHOI

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

Abstract translation: 薄膜晶体管阵列面板包括：栅线; 数据线与栅极线绝缘和交叉; 以及设置在栅极线与数据线交叉的显示区域外的短路棒。 短路棒重叠布置在显示区域外部的数据线的部分。 短路棒包括半导体材料。

公开(公告)号：US20170053800A1

公开(公告)日：2017-02-23

申请号：US15290715

申请日：2016-10-11

Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (Kobe Steel, Ltd.) ,  Samsung Display Co. , Ltd.

Inventor： Hiroaki TAO ,  Aya MIKI ,  Shinya MORITA ,  Satoshi YASUNO ,  Toshihiro KUGIMIYA ,  Jae Woo PARK ,  Je Hun LEE ,  Byung Du AHN ,  Gun Hee KIM

IPC: H01L21/02 ,  H01L21/477

CPC classification number: H01L21/02554 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02587 ,  H01L21/02631 ,  H01L21/477 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7869

Abstract: The oxide of the present invention for thin-film transistors is an In—Zn—Sn-based oxide containing In, Zn, and Sn, wherein when the respective contents (atomic %) of metal elements contained in the In—Zn—Sn-based oxide are expressed by [Zn], [Sn], and [In], the In—Zn—Sn-based oxide fulfills the following expressions (2) and (4) when [In]/([In]+[Sn])≦0.5; or the following expressions (1), (3), and (4) when [In]/([In]+[Sn])>0.5. [In]/([In]+[Zn]+[Sn])≦0.3 - - - (1), [In]/([In]+[Zn]+[Sn])≦1.4×{[Zn]/([Zn]+[Sn])}−0.5 - - - (2), [Zn]/([In]+[Zn]+[Sn])≦0.83 - - - (3), and 0.1≦[In]/([In]+[Zn]+[Sn]) - - - (4). According to the present invention, oxide thin films for thin-film transistors can be obtained, which provide TFTs with excellent switching characteristics, and which have high sputtering rate in the sputtering and properly controlled etching rate in the wet etching.

Abstract translation: 用于薄膜晶体管的本发明的氧化物是含有In，Zn和Sn的In-Zn-Sn系氧化物，其中，当In-Zn-Sn系中含有的金属元素的含量（原子％ 当[In] /（[In] + [Sn]）[Zn]，[In] + [Sn]表示[Zn]，[Sn]和[In]时，In-Zn-Sn系氧化物满足下述（2） ]）≤0.5; 当[In] /（[In] + [Sn]）> 0.5时，或以下表达式（1），（3）和（4）。 [In] /（[In] + [Zn] + [Sn]）≤0.3 - - - （1），[In] /（[In] + [Zn] + [Sn]）≤1.4×{[Zn] /([Zn]+[Sn])}-0.5 - - - （2），[Zn] /（[In] + [Zn] + [Sn]）≤0.83 - - - （3）和0.1≤[ In] /（[In] + [Zn] + [Sn]） - - - （4）。 根据本发明，可以获得用于薄膜晶体管的氧化物薄膜，其提供具有优异的开关特性的TFT，并且在溅射中具有高溅射速率并且在湿蚀刻中具有适当控制的蚀刻速率。

公开(公告)号：US20130299817A1

公开(公告)日：2013-11-14

申请号：US13660362

申请日：2012-10-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jae Woo PARK ,  Do-Hyun Kim ,  Young Joo Choi ,  Dong Hoon Lee ,  Sung Haeng Cho

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

公开(公告)号：US20160322507A1

公开(公告)日：2016-11-03

申请号：US15137476

申请日：2016-04-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： June Whan CHOI ,  Jun Hyuck JEON ,  Seung-Kyeng CHO ,  Jang Soo KIM ,  Jae Woo PARK ,  Ki Seong SEO ,  Soo Woong LEE ,  Jeong Young LEE

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24

CPC classification number: H01L29/78606 ,  H01L21/28008 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/45 ,  H01L29/458 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor array panel, including a substrate; a gate electrode on the substrate; a semiconductor layer on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer including a first oxide insulating layer in contact with the semiconductor layer; a source electrode on the semiconductor layer; a drain electrode facing the source electrode; and a passivation layer covering the source electrode and the drain electrode, the passivation layer including a second oxide insulating layer in contact with the source electrode and the drain electrode, at least one of the first oxide insulating layer and the second oxide insulating layer having a varying hydrogen content distribution in a thickness direction.

Abstract translation: 一种薄膜晶体管阵列面板，包括基板; 基板上的栅电极; 衬底上的半导体层; 在所述栅极电极和所述半导体层之间的栅极绝缘层，所述栅极绝缘层包括与所述半导体层接触的第一氧化物绝缘层; 半导体层上的源电极; 面向源电极的漏电极; 以及覆盖所述源电极和所述漏电极的钝化层，所述钝化层包括与所述源电极和所述漏电极接触的第二氧化物绝缘层，所述第一氧化物绝缘层和所述第二氧化物绝缘层中的至少一个具有 在厚度方向上变化的氢含量分布。

公开(公告)号：US20150200212A1

公开(公告)日：2015-07-16

申请号：US14466317

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu XUN ,  Jae Woo PARK ,  Jae Won SONG ,  Keum Hee LEE ,  June Whan CHOI

IPC: H01L27/12 ,  H01L21/443 ,  H01L21/4763 ,  H01L29/45 ,  H01L29/417

CPC classification number: H01L27/124 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/443 ,  H01L21/76852 ,  H01L23/53238 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

Abstract translation: 如下提供薄膜晶体管阵列面板。 栅电极设置在基板上。 半导体层设置在栅电极上。 栅极绝缘层设置在栅电极和半导体层之间。 源电极设置在半导体层的第一侧上，具有第一侧表面。 漏电极设置在半导体层的第二侧上，具有第二侧表面。 第一和第二侧表面限定了与栅电极重叠的间隔。 金属硅化物层设置在第一和第二侧表面上。 在金属硅化物层，源电极和漏电极上设置钝化层。 钝化层不与第一和第二侧表面接触。

公开(公告)号：US20130306972A1

公开(公告)日：2013-11-21

申请号：US13725333

申请日：2012-12-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young RYU ,  Ki Won KIM ,  Jae Woo PARK ,  Kap Soo YOON ,  Young Joo CHOI

IPC: H01L29/786 ,  H01L33/08

CPC classification number: H01L29/786 ,  H01L27/1225 ,  H01L27/124 ,  H01L33/08

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：基板; 位于基板上的栅极线; 位于栅极线上的栅极绝缘层; 位于所述栅极绝缘层上且具有沟道部分的半导体层; 包括源电极和漏电极的数据线，所述源极和漏极都位于所述半导体层上; 位于数据线和漏电极上并具有形成在其中的接触孔的钝化层; 位于所述钝化层上的像素电极，其中所述像素电极在所述接触孔内接触所述漏电极，并且所述半导体层的沟道部分和所述接触孔在所述衬底的平面图中与所述栅极线重叠。