公开(公告)号：US20150049276A1

公开(公告)日：2015-02-19

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young CHOI ,  Bo Sung KIM ,  Jae Woo PARK ,  Hee Jun BYEON ,  Young-Wook LEE ,  Moon-Keun CHOI

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

Abstract translation: 薄膜晶体管阵列面板包括：栅线; 数据线与栅极线绝缘和交叉; 以及设置在栅极线与数据线交叉的显示区域外的短路棒。 短路棒重叠布置在显示区域外部的数据线的部分。 短路棒包括半导体材料。

公开(公告)号：US20150162251A1

公开(公告)日：2015-06-11

申请号：US14253040

申请日：2014-04-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yeon Taek JEONG ,  Hee Jun BYEON

IPC: H01L21/66 ,  H01L27/12

CPC classification number: H01L27/1259 ,  H01L22/34 ,  H01L27/124 ,  H01L27/3244 ,  H01L27/3276 ,  H01L51/0031

Abstract: A display device includes a first insulating substrate including a display area, a peripheral area and a test area, a gate conductor including a test element group gate electrode, a gate electrode and a gate line on the first insulating substrate, a gate insulating layer on the gate conductor, a semiconductor layer including a test element group semiconductor layer and a pixel semiconductor layer on the gate insulating layer, a data conductor including a test element group source electrode, a test element group drain electrode, a data line including a source electrode, and a drain electrode on the semiconductor layer, a first passivation layer on the data conductor, a test element group common electrode and a pixel common electrode on the first passivation layer, a second passivation layer on the test element group common electrode and the pixel common electrode, and a pixel electrode on the second passivation layer.

Abstract translation: 显示装置包括：第一绝缘基板，包括显示区域，外围区域和测试区域;在第一绝缘基板上包括测试元件组栅电极，栅极电极和栅极线的栅极导体，栅绝缘层， 栅极导体，包括测试元件组半导体层和栅极绝缘层上的像素半导体层的半导体层，包括测试元件组源电极，测试元件组漏电极，包括源电极的数据线的数据导体 以及半导体层上的漏电极，数据导体上的第一钝化层，第一钝化层上的测试元件组公共电极和像素公共电极，测试元件组公共电极上的第二钝化层和像素 公共电极和第二钝化层上的像素电极。

公开(公告)号：US20160027805A1

公开(公告)日：2016-01-28

申请号：US14875320

申请日：2015-10-05

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Hye Young RYU ,  Hee Jun BYEON ,  Woo Geun LEE ,  Kap Soo YOON ,  Yoon Ho KIM ,  Chun Won BYUN

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/127 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262

Abstract: A thin film transistor array panel and a manufacturing method thereof according to an exemplary embodiment of the present invention form a contact hole in a second passivation layer formed of an organic insulator, protect a side of the contact hole by covering with a protection member formed of the same layer as the first field generating electrode and formed of a transparent conductive material, and etch the first passivation layer below the second passivation layer using the protection member as a mask. Therefore, it is possible to prevent the second passivation layer formed of an organic insulator from being overetched while etching the insulating layer below the second passivation layer so that the contact hole is prevented from being made excessively wide.

公开(公告)号：US20150162349A1

公开(公告)日：2015-06-11

申请号：US14456154

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Hee Jun BYEON ,  Seung Sok SON ,  Bo Sung KIM ,  Yeon Taek JEONG

IPC: H01L27/12 ,  H01L21/311

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1259

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 栅极线和公共电压线，并且彼此电分离; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的第一钝化层; 在第一钝化层上的公共电极; 公共电极上的第二钝化层; 以及第二钝化层上的像素电极和连接构件，并且彼此电分离。 在第一钝化层和第二钝化层中限定第一接触孔和第二接触孔。 像素电极和漏极通过第二接触孔相互连接。 连接构件和公共电极通过第一接触孔彼此连接。