公开(公告)号：US20210036076A1

公开(公告)日：2021-02-04

申请号：US16895756

申请日：2020-06-08

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seul Ki KIM ,  Seung Sok SON ,  Kap Soo YOON ,  Woo Geun LEE ,  Su Jung JUNG ,  Seung Ha CHOI

IPC: H01L27/32

Abstract: A display device includes a substrate having a display area and a pad area. A gate conductive layer disposed on the substrate includes a gate conductive metal layer and a gate capping layer. The gate conductive layer forms a gate electrode in the display area and a wire pad in the pad area that is exposed by a pad opening. An interlayer insulating film disposed on the gate conductive layer covers the gate electrode. A data conductive layer disposed on the interlayer insulating film in the display area includes source and drain electrodes. A passivation layer disposed on the data conductive layer covers the source and drain electrodes. A via layer is disposed on the passivation layer. A pixel electrode is disposed on the via layer. The pixel electrode is connected to the source electrode through a contact hole penetrating the via layer and the passivation layer.

公开(公告)号：US20160027802A1

公开(公告)日：2016-01-28

申请号：US14552619

申请日：2014-11-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Ouck AHN ,  Seung Sok SON

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1259

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line electrically separated from each other and elongated parallel with each other on the substrate; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connection member on the second passivation layer and electrically separated from each other. The connection member is elongated in a horizontal direction parallel with the gate line and connects the common voltage line and the common electrode to each other.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 栅极线和公共电压线彼此电分离并在基板上彼此平行延伸; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的第一钝化层; 在第一钝化层上的公共电极; 公共电极上的第二钝化层; 以及在第二钝化层上的像素电极和连接构件，并且彼此电分离。 连接构件在与栅极线平行的水平方向上伸长并将公共电压线和公共电极彼此连接。

公开(公告)号：US20240120342A1

公开(公告)日：2024-04-11

申请号：US18208263

申请日：2023-06-10

Applicant: Samsung Display Co., LTD.

Inventor： Sung Gwon MOON ,  Dong Han KANG ,  Jee Hoon KIM ,  Seung Sok SON ,  Shin Hyuk YANG ,  Woo Geun LEE

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/127

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

公开(公告)号：US20220139965A1

公开(公告)日：2022-05-05

申请号：US17368200

申请日：2021-07-06

Applicant: Samsung Display Co., Ltd.

Inventor： Woo Bin LEE ,  Seok Hwan BANG ,  Seung Sok SON ,  Woo Geun LEE ,  Soo Jung CHAE

IPC: H01L27/12

Abstract: A display device includes a substrate and a transistor disposed on the substrate and including a semiconductor layer, wherein the semiconductor layer includes a mesh structure, and wherein a plurality of openings are formed in the semiconductor layer.

公开(公告)号：US20220140059A1

公开(公告)日：2022-05-05

申请号：US17475950

申请日：2021-09-15

Applicant: Samsung Display Co., LTD.

Inventor： Jong In KIM ,  Hyun Seong KANG ,  Joon Geol KIM ,  Seung Sok SON ,  Woo Geun LEE ,  Young Jae JEON ,  Soo Jung CHAE ,  Ji Yun HONG

IPC: H01L27/32 ,  H01L51/00

Abstract: A display device includes a pixel electrode disposed on a first surface of a substrate, a light emitting layer disposed on the pixel electrode, a common electrode disposed on the light emitting layer, a supply voltage line disposed on the first surface of the substrate and applying a voltage to the common electrode, a first auxiliary conductive layer disposed on a second surface of the substrate, and a first connection conductive layer at least partially disposed on a side surface of the substrate and electrically connecting the first auxiliary conductive layer to the supply voltage line.

公开(公告)号：US20220102390A1

公开(公告)日：2022-03-31

申请号：US17342088

申请日：2021-06-08

Applicant: Samsung Display Co., LTD.

Inventor： Keum Hee LEE ,  Dong Hoon SHIN ,  June Whan CHOI ,  Seung Sok SON ,  Woo Geun LEE

IPC: H01L27/12

Abstract: A display device includes a base layer; a first pattern disposed on the base layer; an insulating layer disposed on the first pattern and including layers; and a second pattern disposed on the insulating layer. At least two of the layers of the insulating layer include a same material.

公开(公告)号：US20150162349A1

公开(公告)日：2015-06-11

申请号：US14456154

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Hee Jun BYEON ,  Seung Sok SON ,  Bo Sung KIM ,  Yeon Taek JEONG

IPC: H01L27/12 ,  H01L21/311

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1259

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 栅极线和公共电压线，并且彼此电分离; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的第一钝化层; 在第一钝化层上的公共电极; 公共电极上的第二钝化层; 以及第二钝化层上的像素电极和连接构件，并且彼此电分离。 在第一钝化层和第二钝化层中限定第一接触孔和第二接触孔。 像素电极和漏极通过第二接触孔相互连接。 连接构件和公共电极通过第一接触孔彼此连接。

公开(公告)号：US20240431161A1

公开(公告)日：2024-12-26

申请号：US18398191

申请日：2023-12-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jong In KIM ,  Hyun Seong KANG ,  Yoo Mi RA ,  Seung Sok SON ,  Kap Soo YOON ,  Keum Hee LEE ,  Doo Young LEE ,  Seong Young LEE ,  Woo Geun LEE ,  Ji Yun HONG

IPC: H10K59/131 ,  G09G3/3233 ,  H10K59/121

Abstract: A display device is provided. The display device comprises a first voltage line, a data line, a first capacitor electrode, a buffer layer disposed on the first voltage line, a second capacitor electrode disposed on the first capacitor electrode to overlap the first capacitor electrode in a plan view, a first transistor disposed on the buffer layer and connected to the data line, an interlayer insulating layer disposed on the second capacitor electrode, and a first connection pattern disposed on the interlayer insulating layer and connected to the second capacitor electrode and the first transistor, wherein the first connection pattern is connected to the second capacitor electrode through a contact hole formed through the interlayer insulating layer and connected to the first transistor through a contact hole formed through the interlayer insulating layer, and the first capacitor electrode overlaps the first connection pattern.

公开(公告)号：US20240324320A1

公开(公告)日：2024-09-26

申请号：US18517068

申请日：2023-11-22

Applicant: Samsung Display Co., LTD.

Inventor： Ki Won KIM ,  Jeong Ju PARK ,  Seung Sok SON ,  Kap Soo YOON ,  Woo Geun LEE ,  Ji Yun HONG

IPC: H10K59/123 ,  H10K59/12 ,  H10K71/60

CPC classification number: H10K59/123 ,  H10K59/1201 ,  H10K71/60

Abstract: A method for fabricating a display device includes providing a substrate into a chamber; forming an active material layer on the substrate by a plurality of deposition processes in the chamber; forming an active layer by patterning the active material layer: forming a transistor including a gate electrode overlapping the active layer; and forming a pixel electrode on the transistor, at least two deposition processes among the plurality of deposition processes are performed by applying different magnitudes of power, respectively.

公开(公告)号：US20240122006A1

公开(公告)日：2024-04-11

申请号：US18238550

申请日：2023-08-28

Applicant: Samsung Display Co., LTD.

Inventor： Shin Hyuk YANG ,  Dong Han KANG ,  Jee Hoon KIM ,  Sung Gwon MOON ,  Seung Sok SON ,  Woo Geun LEE

IPC: H10K59/131 ,  H10K59/12 ,  H10K59/122

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K59/122

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.