公开(公告)号：US20130328042A1

公开(公告)日：2013-12-12

申请号：US13679910

申请日：2012-11-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Doo Hyoung LEE ,  Chan Woo YANG ,  Seung-Ho JUNG ,  Doo Na KIM ,  Bo Sung KIM ,  Eun Hye PARK ,  June Whan CHOI

IPC: H01L29/786 ,  H01B1/06 ,  H01L29/66

CPC classification number: H01L29/66969 ,  H01B1/06 ,  H01L21/02565 ,  H01L21/02628 ,  H01L29/7869

Abstract: A thin film transistor substrate according to an exemplary embodiment of the present invention includes a semiconductor layer including metal disposed on an insulating substrate, a gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode overlapping the semiconductor layer, wherein the metal in the semiconductor layer comprises indium (In), zinc (Zn), and tin (Sn), and a molar ratio (R, R[mol %]=[In]/[In+Zn+Sn]/100) of indium (In) to the metals in the semiconductor layer is less than about 20%, and more specifically, the molar ratio (R, R[mol %]=[In]/[In+Zn+Sn]/100) of indium (In) of the metals in the semiconductor layer is about 5% to about 13%.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管基板包括：半导体层，包括设置在绝缘基板上的金属，与半导体层重叠的栅极电极以及与半导体层重叠的源电极和漏电极，其中金属 在半导体层中包含铟（In），锌（Zn）和锡（Sn），并且铟的摩尔比（R，R [mol％] = [In] / [In + Zn + Sn] / 100） （In）/ [In + Zn + Sn] / 100）的摩尔比（R，R [mol％] = [In] / [In + Zn + Sn] / 100）小于约20％ In）的半导体层中的金属为约5％至约13％。

公开(公告)号：US20150162349A1

公开(公告)日：2015-06-11

申请号：US14456154

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Hee Jun BYEON ,  Seung Sok SON ,  Bo Sung KIM ,  Yeon Taek JEONG

IPC: H01L27/12 ,  H01L21/311

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1259

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a common voltage line on the substrate and electrically separated from each other; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connecting member on the second passivation layer and electrically separated from each other. A first contact hole and a second contact hole are defined in the first and second passivation layers. The pixel electrode and the drain electrode are connected to each other through the second contact hole. The connecting member and the common electrode are connected to each other through the first contact hole.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 栅极线和公共电压线，并且彼此电分离; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的第一钝化层; 在第一钝化层上的公共电极; 公共电极上的第二钝化层; 以及第二钝化层上的像素电极和连接构件，并且彼此电分离。 在第一钝化层和第二钝化层中限定第一接触孔和第二接触孔。 像素电极和漏极通过第二接触孔相互连接。 连接构件和公共电极通过第一接触孔彼此连接。

公开(公告)号：US20150008437A1

公开(公告)日：2015-01-08

申请号：US14495835

申请日：2014-09-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yeon Taek JEONG ,  Bo Sung KIM ,  Doo-Hyoung LEE ,  June Whan CHOI ,  Tae-Young CHOI ,  Kano MASATAKA

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

Abstract: A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

Abstract translation: 提供薄膜晶体管。 根据本发明的示例性实施例的薄膜晶体管包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 半导体层，设置在所述基板上，并且至少包括与所述栅电极重叠的部分; 设置在所述栅极线和所述半导体层之间的栅极绝缘层; 以及设置在所述基板上并且在所述半导体层的沟道区域上彼此面对的源电极和漏电极。 栅极绝缘层包括第一区域和第二区域，第一区域对应于半导体层的沟道区域，第一区域由第一材料制成，第二区域由第二材料制成，第一材料 并且第二材料具有不同的碳和硅原子数比。

公开(公告)号：US20150049276A1

公开(公告)日：2015-02-19

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young CHOI ,  Bo Sung KIM ,  Jae Woo PARK ,  Hee Jun BYEON ,  Young-Wook LEE ,  Moon-Keun CHOI

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

Abstract translation: 薄膜晶体管阵列面板包括：栅线; 数据线与栅极线绝缘和交叉; 以及设置在栅极线与数据线交叉的显示区域外的短路棒。 短路棒重叠布置在显示区域外部的数据线的部分。 短路棒包括半导体材料。