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    Electronic device with die being sunk in substate
    1.
    发明授权
    Electronic device with die being sunk in substate 有权

    公开(公告)号：US10211140B2

    公开(公告)日：2019-02-19

    申请号：US15616009

    申请日：2017-06-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

    IPC: H01L23/498 ,  H01L23/367 ,  H01L21/52 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

    Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

    Semiconductor device and corresponding method
    5.
    发明授权
    Semiconductor device and corresponding method 有权

    公开(公告)号：US11152289B2

    公开(公告)日：2021-10-19

    申请号：US16406911

    申请日：2019-05-08

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Michele Derai

    IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

    Method of integrating capacitors on lead frame in semiconductor devices
    6.
    发明授权
    Method of integrating capacitors on lead frame in semiconductor devices 有权

    公开(公告)号：US10283441B2

    公开(公告)日：2019-05-07

    申请号：US15282619

    申请日：2016-09-30

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L49/02

    Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.

    SHIELDED ENCAPSULATING STRUCTURE AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    SHIELDED ENCAPSULATING STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    其屏蔽结构及其制造方法

    公开(公告)号：US20150217993A1

    公开(公告)日：2015-08-06

    申请号：US14686540

    申请日：2015-04-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio Fontana ,  Giovanni Graziosi ,  Alex Gritti

    IPC: B81B7/00 ,  H05K9/00

    CPC classification number: B81B7/0064 ,  B81B2201/0257 ,  H01L2224/48091 ,  H01L2224/48137 ,  H04R1/021 ,  H04R1/04 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2201/029 ,  H05K9/0009 ,  H01L2924/00014

    Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.

    Abstract translation: 一个或多个实施例涉及封装结构，包括：具有第一表面并且容纳至少一个导电焊盘的衬底，所述至少一个导电焊盘面向第一表面延伸并且被配置为在参考电压下电耦合到导通端子; 盖构件，其设置在离基板的第一表面一定距离处; 以及在基板和盖构件之间延伸的壳体壁。 衬底，盖构件和壳体壁限定空腔，其在封装结构内部并容纳导电垫。 此外，在腔内部还存在至少一个导电结构，其在盖构件和导电垫之间延伸并与之电接触，用于将盖构件电连接到导电端子。

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