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1.发明授权公开(公告)号：US12021052B2
公开(公告)日：2024-06-25
申请号：US17158781
申请日：2021-01-26
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana
IPC: H01L21/56 , G01N21/956 , H01L23/00 , H01L23/31 , H01L25/065
CPC classification number: H01L24/19 , G01N21/95684 , H01L21/565 , H01L23/3185 , H01L24/11 , H01L24/13 , H01L24/20 , H01L25/0652
Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.
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公开(公告)号：US11152289B2
公开(公告)日：2021-10-19
申请号：US16406911
申请日：2019-05-08
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Fulvio Vittorio Fontana , Giovanni Graziosi , Michele Derai
IPC: H01L23/495 , H01L23/00 , H01L21/48
Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
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公开(公告)号：US10283441B2
公开(公告)日：2019-05-07
申请号：US15282619
申请日：2016-09-30
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Fulvio Vittorio Fontana , Giovanni Graziosi
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/31 , H01L49/02
Abstract: In an embodiment, a method of integrating capacitors in semiconductor devices includes: providing a lead-frame for a semiconductor device, the lead-frame including one or more electrically conductive areas, forming a dielectric layer over the electrically conductive area or areas, forming an electrically conductive layer over the dielectric layer thus forming one or more capacitors including the dielectric layer sandwiched between an electrically conductive area and the electrically conductive layer, and arranging a semiconductor die onto the lead-frame by providing electrical contact between the semiconductor die and the electrically conductive layer.
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公开(公告)号：US10128057B2
公开(公告)日：2018-11-13
申请号：US15164702
申请日：2016-05-25
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Mario Giovanni Scurati , Marco Morelli , Fulvio Vittorio Fontana
Abstract: A supercapacitor including: a shell; a chamber in the shell; a first electrode and a second electrode on respective walls of the chamber; and a separator arranged between the first electrode and the second electrode through the chamber. The separator includes a first perforated membrane and a second perforated membrane, which is movable with respect to the first membrane between a first position, in which the first membrane and the second membrane are separate and a second position, in which the first membrane and the second membrane are in contact and coupled for rendering the separator impermeable.
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公开(公告)号：US09972562B2
公开(公告)日：2018-05-15
申请号：US15471472
申请日：2017-03-28
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Fulvio Vittorio Fontana
IPC: H01L23/495 , H01L21/48
CPC classification number: H01L23/49568 , H01L21/4825 , H01L21/4832 , H01L21/4842 , H01L23/3107 , H01L23/4334 , H01L23/49503 , H01L23/4952 , H01L23/49541 , H01L23/49575 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/97 , H01L2924/181 , H01L2924/00012
Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.
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Patent Agency Ranking
公开(公告)号：US09841341B2
公开(公告)日：2017-12-12
申请号：US14861648
申请日：2015-09-22
Applicant: STMICROELECTRONICS S.R.L. , STMICROELECTRONICS, INC.
Inventor： Fulvio Vittorio Fontana , Jefferson Talledo
IPC: H01L21/50 , H01L23/498 , G01L19/14 , B81B7/00 , B81C1/00 , H01L23/057 , H01L23/495
CPC classification number: G01L19/148 , B81B7/0045 , B81C1/00325 , H01L21/50 , H01L23/057 , H01L23/49575 , H01L23/49861 , H01L2224/48091 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014
Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.
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公开(公告)号：US20150217993A1
公开(公告)日：2015-08-06
申请号：US14686540
申请日：2015-04-14
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana , Giovanni Graziosi , Alex Gritti
CPC classification number: B81B7/0064 , B81B2201/0257 , H01L2224/48091 , H01L2224/48137 , H04R1/021 , H04R1/04 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2201/029 , H05K9/0009 , H01L2924/00014
Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.
Abstract translation: 一个或多个实施例涉及封装结构，包括：具有第一表面并且容纳至少一个导电焊盘的衬底，所述至少一个导电焊盘面向第一表面延伸并且被配置为在参考电压下电耦合到导通端子; 盖构件，其设置在离基板的第一表面一定距离处; 以及在基板和盖构件之间延伸的壳体壁。 衬底，盖构件和壳体壁限定空腔，其在封装结构内部并容纳导电垫。 此外，在腔内部还存在至少一个导电结构，其在盖构件和导电垫之间延伸并与之电接触，用于将盖构件电连接到导电端子。
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公开(公告)号：US20130105952A1
公开(公告)日：2013-05-02
申请号：US13659753
申请日：2012-10-24
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana , Giovanni Graziosi , Alex Gritti
CPC classification number: B81B7/0064 , B81B2201/0257 , H01L2224/48091 , H01L2224/48137 , H04R1/021 , H04R1/04 , H04R19/005 , H04R19/04 , H04R31/006 , H04R2201/003 , H04R2201/029 , H05K9/0009 , H01L2924/00014
Abstract: One or more embodiments are directed to encapsulating structure comprising: a substrate having a first surface and housing at least one conductive pad, which extends facing the first surface and is configured for being electrically coupled to a conduction terminal at a reference voltage; a cover member, set at a distance from and facing the first surface of the substrate; and housing walls, which extend between the substrate and the cover member. The substrate, the cover member, and the housing walls define a cavity, which is internal to the encapsulating structure and houses the conductive pad. Moreover present inside the cavity is at least one electrically conductive structure, which extends between, and in electrical contact with, the cover member and the conductive pad for connecting the cover member electrically to the conduction terminal.
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公开(公告)号：US11515240B2
公开(公告)日：2022-11-29
申请号：US16940815
申请日：2020-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fulvio Vittorio Fontana
IPC: H01L23/495 , H01L23/00 , H01L23/31 , H01L21/56
Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.
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公开(公告)号：US11004775B2
公开(公告)日：2021-05-11
申请号：US16782797
申请日：2020-02-05
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Cristina Somma , Fulvio Vittorio Fontana
IPC: H01L23/495
Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
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