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1.发明申请METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT 有权处理交易方法，相关系统和计算机程序产品公开(公告)号：US20140289439A1
公开(公告)日：2014-09-25
申请号：US14219850
申请日：2014-03-19
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F13/40
CPC classification number: G06F13/4027 , G06F13/14 , G06F15/7825 , G06F2213/0038 , H04Q2213/13399 , H04Q2213/399
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
Abstract translation: 诸如片上系统的系统包括通过IP块生成交易的接口组件或PLUG，诸如通过虚拟通道服务于一个或多个客户端的互连。 客户端或客户端通过客户端/虚拟通道映射映射到虚拟通道。 虚拟通道被提供为与IP块中的第二组虚拟通道协作的接口组件中的第一组虚拟通道。 提供了第一组虚拟通道和第二组虚拟通道的第一和第二客户端/虚拟通道映射。 第一个和第二个客户端/虚拟通道映射是单独可编程的，并且彼此相互解耦。
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公开(公告)号：US20130268990A1
公开(公告)日：2013-10-10
申请号：US13789445
申请日：2013-03-07
Inventor： Ignazio Antonino Urzi , Rene Peyrard , Daniele Mangano
IPC: H04L12/24
CPC classification number: H04L41/5038 , H04L41/0896 , H04L41/5025 , H04L43/0882 , H04L47/20 , H04L47/22 , H04L47/2416
Abstract: A method includes providing at least one target bandwidth for bandwidth usage on an interconnect, the target bandwidth being for traffic associated with a traffic initiator. The method also includes measuring a served bandwidth and resetting the measuring of served bandwidth in response to an occurrence of an event.
Abstract translation: 一种方法包括为互连上的带宽使用提供至少一个目标带宽，所述目标带宽用于与业务发起者相关联的流量。 该方法还包括测量服务带宽并且响应于事件的发生重置服务带宽的测量。
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公开(公告)号：US20210265949A1
公开(公告)日：2021-08-26
申请号：US17180748
申请日：2021-02-20
Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.
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公开(公告)号：US10102171B2
公开(公告)日：2018-10-16
申请号：US15608857
申请日：2017-05-30
Inventor： Daniele Mangano , Ignazio Antonino Urzi
Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.
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公开(公告)号：US11764731B2
公开(公告)日：2023-09-19
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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Patent Agency Ranking
公开(公告)号：US11239796B2
公开(公告)日：2022-02-01
申请号：US17180748
申请日：2021-02-20
Abstract: An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.
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公开(公告)号：US20140112149A1
公开(公告)日：2014-04-24
申请号：US14059252
申请日：2013-10-21
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Ignazio Antonino Urzi , Nicolas Graciannette , Daniele Mangano
IPC: H04L12/835
CPC classification number: H04L47/30 , G06F15/7825 , H04L47/12 , H04L47/263 , Y02D50/10
Abstract: An apparatus includes an output configured to output data to a communication path of an interconnect for routing to a target and a rate controller configured to control a rate of the output data. The rate controller is configured to control the rate in response to feedback information from the target.
Abstract translation: 一种装置包括被配置为将数据输出到用于路由到目标的互连的通信路径的输出和被配置为控制输出数据的速率的速率控制器。 速率控制器被配置为响应于来自目标的反馈信息来控制速率。
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公开(公告)号：US20230087239A1
公开(公告)日：2023-03-23
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11496170B2
公开(公告)日：2022-11-08
申请号：US17180751
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
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公开(公告)号：US10019399B2
公开(公告)日：2018-07-10
申请号：US14940026
申请日：2015-11-12
Inventor： Daniele Mangano , Ignazio Antonino Urzi
IPC: G06F17/50 , G06F13/36 , H04L12/933 , G06F15/78 , H04L12/935 , G06F13/40
CPC classification number: G06F13/36 , G06F13/4068 , G06F15/7807 , G06F15/7825 , G06F17/5077 , G06F2217/04 , G06F2217/06 , H04L49/109 , H04L49/15 , H04L49/3009
Abstract: A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
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