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1.发明授权公开(公告)号：US09252130B2
公开(公告)日：2016-02-02
申请号：US13853810
申请日：2013-03-29
Applicant: STATS ChipPAC, Ltd.
Inventor： KyungMoon Kim , YoungChul Kim , HunTeak Lee , KeonTaek Kang , HeeJo Chi
IPC: H01L25/065 , H01L23/31 , H01L23/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/2919 , H01L2224/32225 , H01L2224/48145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73207 , H01L2224/75251 , H01L2224/75252 , H01L2224/75704 , H01L2224/75705 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83192 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/12043 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
Abstract translation: 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。
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2.发明申请Methods of Manufacturing Flip Chip Semiconductor Packages Using Double-Sided Thermal Compression Bonding 有权使用双面热压缩接合制造倒装芯片半导体封装的方法公开(公告)号：US20140295618A1
公开(公告)日：2014-10-02
申请号：US13853810
申请日：2013-03-29
Applicant: STATS CHIPPAC, LTD.
Inventor： KyungMoon Kim , YoungChul Kim , HunTeak Lee , KeonTaek Kang , HeeJo Chi
IPC: H01L23/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/13023 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/2919 , H01L2224/32225 , H01L2224/48145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73207 , H01L2224/75251 , H01L2224/75252 , H01L2224/75704 , H01L2224/75705 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83192 , H01L2224/9211 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00011 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H01L2924/12043 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Methods of producing a semiconductor package using dual-sided thermal compression bonding includes providing a substrate having an upper surface and a lower surface. A first device having a first surface and a second surface can be provided along with a second device having a third surface and a fourth surface. The first surface of the first device can be coupled to the upper surface of the substrate while the third surface of the second device can be coupled to the lower surface of the substrate, the coupling occurring simultaneously to produce the semiconductor package.
Abstract translation: 使用双面热压接的半导体封装的制造方法包括提供具有上表面和下表面的基板。 具有第一表面和第二表面的第一装置可以与具有第三表面和第四表面的第二装置一起提供。 第一器件的第一表面可以耦合到衬底的上表面，而第二器件的第三表面可以耦合到衬底的下表面，耦合同时发生以产生半导体封装。
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3.发明授权Semiconductor device and method of individual die bonding followed by simultaneous multiple die thermal compression bonding 有权半导体器件和单个芯片接合的方法，然后同时进行多芯片热压接公开(公告)号：US09524958B2
公开(公告)日：2016-12-20
申请号：US13928862
申请日：2013-06-27
Applicant: STATS ChipPAC, Ltd.
Inventor： JoonYoung Choi , YongHee Kang , HunTeak Lee , KeonTaek Kang , YoungChul Kim
CPC classification number: H01L25/50 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2224/12105 , H01L2224/16225 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.
Abstract translation: 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。
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4.发明申请Semiconductor Device and Method of Individual Die Bonding Followed by Simultaneous Multiple Die Thermal Compression Bonding 有权半导体器件和单个模具接合的方法，随后是同时多模热压接合公开(公告)号：US20150001703A1
公开(公告)日：2015-01-01
申请号：US13928862
申请日：2013-06-27
Applicant: STATS ChipPAC, Ltd.
Inventor： JoonYoung Choi , YongHee Kang , HunTeak Lee , KeonTaek Kang , YoungChul Kim
IPC: H01L25/00 , H01L25/065
CPC classification number: H01L25/50 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/0655 , H01L2224/12105 , H01L2224/16225 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.
Abstract translation: 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。
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