公开(公告)号：US10720402B2

公开(公告)日：2020-07-21

申请号：US15316574

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： Makoto Murai ,  Kazuki Sato ,  Hiroyuki Yamada ,  Yuji Takaoka ,  Makoto Imai ,  Shigeki Amano

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L25/065

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.

公开(公告)号：US20140205046A1

公开(公告)日：2014-07-24

申请号：US14153252

申请日：2014-01-13

Applicant: Sony Corporation

Inventor： Keiji Morikawa ,  Satoshi Kametani ,  Makoto Imai ,  Kazumasa Nishimoto

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/12

Abstract: A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data.

Abstract translation: 源装置包括：低速数据供给部，被配置为将具有不同频率的时钟信号中的低时钟信号同步地产生的数据作为低速数据提供，低频时钟信号的频率低于预定的频率 值; 高速数据提供部，被配置为提供与时钟信号不同的高时钟信号产生的数据作为高速数据，高频时钟信号的频率高于低时钟信号的频率; 分配部分，被配置为根据高和低时钟信号的频率之间的比例将低速数据划分成预定数量的数据; 以及数据发送部，被配置为将高速数据和分割的低速数据片段存储在具有预定数据大小的数据中，并发送存储的数据。

公开(公告)号：US09069490B2

公开(公告)日：2015-06-30

申请号：US14153252

申请日：2014-01-13

Applicant: Sony Corporation

Inventor： Keiji Morikawa ,  Satoshi Kametani ,  Makoto Imai ,  Kazumasa Nishimoto

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/12

Abstract: A source device includes: a low-speed data supply section configured to supply, as low-speed data, data generated in synchronization with a low clock signal out of clock signals having different frequencies, the low clock signal having a frequency lower than a predetermined value; a high-speed data supply section configured to supply, as high-speed data, data generated in synchronization with a high clock signal out of the clock signals, the high clock signal having a frequency higher than that of the low clock signal; a dividing section configured to divide the low-speed data into a predetermined number of pieces of data in accordance with a ratio between the frequencies of the high and low clock signals; and a data transmitting section configured to store the high-speed data and the divided pieces of low-speed data in data having a predetermined data size, and to transmit the stored data.

Abstract translation: 源装置包括：低速数据供给部，被配置为将具有不同频率的时钟信号中的低时钟信号同步地产生的数据作为低速数据提供，低频时钟信号的频率低于预定的频率 值; 高速数据提供部，被配置为提供与时钟信号不同的高时钟信号产生的数据作为高速数据，高频时钟信号的频率高于低时钟信号的频率; 分配部分，被配置为根据高和低时钟信号的频率之间的比例将低速数据划分成预定数量的数据; 以及数据发送部，被配置为将高速数据和分割的低速数据片段存储在具有预定数据大小的数据中，并发送存储的数据。

公开(公告)号：US10014248B2

公开(公告)日：2018-07-03

申请号：US15316546

申请日：2015-06-05

Applicant: SONY CORPORATION

Inventor： Makoto Murai ,  Yuji Takaoka ,  Hiroyuki Yamada ,  Kazuki Sato ,  Makoto Imai

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13564 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/8112 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.