公开(公告)号：US12131774B2

公开(公告)日：2024-10-29

申请号：US17968082

申请日：2022-10-18

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/401 ,  H10B12/00

CPC classification number: G11C11/4097 ,  G11C7/18 ,  G11C11/401 ,  H10B12/30

Abstract: A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

公开(公告)号：US11355177B2

公开(公告)日：2022-06-07

申请号：US16854382

申请日：2020-04-21

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC: G11C5/06 ,  G11C11/408 ,  H01L27/108 ,  H01L49/02 ,  H01L23/528

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

公开(公告)号：US10170566B2

公开(公告)日：2019-01-01

申请号：US15673032

申请日：2017-08-09

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim

IPC: H01L27/108 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L21/764 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.

公开(公告)号：US09525025B2

公开(公告)日：2016-12-20

申请号：US14858905

申请日：2015-09-18

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim

IPC: H01L27/108 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L27/112

CPC classification number: H01L29/0653 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/11286 ,  H01L29/0638 ,  H01L29/4236 ,  H01L29/7827

Abstract: A semiconductor device including a substrate including an active region and a device isolation region that isolates the active region, and a buried bit line and a buried gate electrode formed in the substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having an formed air gap.

Abstract translation: 一种半导体器件，包括包括有源区的衬底和隔离有源区的器件隔离区，以及形成在衬底中的掩埋位线和掩埋栅电极。 器件隔离区域包括沿第一方向延伸的第一器件隔离区域和沿与第一方向交叉的第二方向延伸并且具有形成的气隙的第二器件隔离区域。

公开(公告)号：US11501827B2

公开(公告)日：2022-11-15

申请号：US16728174

申请日：2019-12-27

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC: G11C11/4097 ,  H01L27/108 ,  G11C7/18 ,  G11C11/401

Abstract: A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

公开(公告)号：US09799659B2

公开(公告)日：2017-10-24

申请号：US15209502

申请日：2016-07-13

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L27/10885 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device may include: a semiconductor substrate comprising a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a conductive shield pillar formed in the device isolation region and connected to the semiconductor substrate. Each of the active regions may include: a body portion formed in the substrate; a pillar floating from the body portion and positioned over the body portion; a side portion provided over a side surface of the pillar and connected to the body portion; and an embedded spacer positioned between the side portion and the pillar, the pillar may be coupled to the substrate through the side portion.

公开(公告)号：US12230313B2

公开(公告)日：2025-02-18

申请号：US18542769

申请日：2023-12-18

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC: G11C11/24 ,  G11C11/408 ,  H01L23/528 ,  H01L49/02 ,  H10B12/00

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

公开(公告)号：US11887654B2

公开(公告)日：2024-01-30

申请号：US17739944

申请日：2022-05-09

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC: G11C7/10 ,  G11C11/408 ,  H01L49/02 ,  H01L23/528 ,  H10B12/00

CPC classification number: G11C11/4085 ,  H01L23/528 ,  H01L28/86 ,  H10B12/30 ,  H10B12/50

Abstract: A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.

公开(公告)号：US10109634B2

公开(公告)日：2018-10-23

申请号：US15258588

申请日：2016-09-07

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim

IPC: H01L29/66 ,  H01L27/105 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L21/764 ,  H01L29/06 ,  H01L29/10 ,  H01L27/108

Abstract: A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench.

公开(公告)号：US09799739B2

公开(公告)日：2017-10-24

申请号：US14858732

申请日：2015-09-18

Applicant: SK hynix Inc.

Inventor： Seung-Hwan Kim

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L21/764 ,  H01L27/108

CPC classification number: H01L29/407 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of active regions; and a buried bit line and a buried gate electrode which are formed in the semiconductor substrate. The device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a shield pillar formed therein.