公开(公告)号：US20140302651A1

公开(公告)日：2014-10-09

申请号：US14308182

申请日：2014-06-18

Applicant: SK HYNIX INC.

Inventor： Hyung Jin PARK

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66666 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/115 ,  H01L29/7827

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括形成单元结构，其中存储节点接触耦合到形成在栅极上的硅层，从而简化了器件的制造过程。 半导体器件包括埋在半导体衬底中的位线; 设置在所述半导体衬底上的与所述位线埋设的多个栅极; 第一插头，其设置在所述栅极之间的下部并且耦合到所述位线; 设置在所述栅极的上部和侧壁上的硅层; 以及耦合到设置在所述栅极上的所述硅层的第二插头。

公开(公告)号：US20130119463A1

公开(公告)日：2013-05-16

申请号：US13734698

申请日：2013-01-04

Applicant: SK HYNIX INC.

Inventor： Hyung Jin PARK

IPC: H01L29/78

CPC classification number: H01L29/66666 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/115 ,  H01L29/7827

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括形成单元结构，其中存储节点接触耦合到形成在栅极上的硅层，从而简化了器件的制造过程。 半导体器件包括埋在半导体衬底中的位线; 设置在所述半导体衬底上的与所述位线埋设的多个栅极; 第一插头，其设置在所述栅极之间的下部并且耦合到所述位线; 设置在所述栅极的上部和侧壁上的硅层; 以及耦合到设置在所述栅极上的所述硅层的第二插头。

公开(公告)号：US20240006333A1

公开(公告)日：2024-01-04

申请号：US17986976

申请日：2022-11-15

Applicant: SK hynix Inc.

Inventor： Seung Won LEE ,  Hyung Jin PARK ,  Han Bit KIM ,  Jeong Woo HONG

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L2223/54426

Abstract: A semiconductor includes an underlayer; a lower core layer spaced apart from the underlayer, the lower core layer including a plurality of lower segments spaced apart from each other in a horizontal direction; an upper core layer spaced apart from the lower core layer, the upper core layer including a plurality of upper segments spaced apart from each other in the horizontal direction; a post pattern vertically penetrating the upper core layer and the lower core layer; a passivation layer surrounding the lower core layer, the upper core layer, and the post pattern; coating layer surrounding the passivation layer; and a support pattern extending in the vertical direction and passing through the lower core layer, the upper core layer, the passivation layer, and the coating layer.

公开(公告)号：US20140327085A1

公开(公告)日：2014-11-06

申请号：US14057919

申请日：2013-10-18

Applicant: SK hynix Inc.

Inventor： Hyung Jin PARK

IPC: H01L27/07

CPC classification number: H01L29/8605 ,  H01L28/20 ,  H01L29/66166

Abstract: A variable resistance device includes a parallel structure. The variable resistance device is formed using a silicon (Si) substrate. In the variable resistance device, a conductive line arranged in a current direction is formed over an impurity region, and a resistance value of the resistance device is precisely adjusted by adjusting a level of a voltage applied to the conductive line. The variable resistance device includes a first impurity region formed in a substrate, a second impurity region formed in the substrate and arranged parallel to the first impurity region, a conductive line formed over the first impurity region, and electrode terminals formed at both longitudinal ends of the second impurity region to be coupled to the second impurity region.

Abstract translation: 可变电阻装置包括并联结构。 可变电阻器件使用硅（Si）衬底形成。 在可变电阻器件中，在杂质区域上形成沿电流方向布置的导电线，并且通过调节施加到导线的电压的电平来精确地调节电阻器件的电阻值。 可变电阻器件包括形成在衬底中的第一杂质区域，形成在衬底中并与第一杂质区平行布置的第二杂质区，形成在第一杂质区上的导线，以及形成在第一杂质区两端的电极端 要耦合到第二杂质区的第二杂质区。

公开(公告)号：US20140061741A1

公开(公告)日：2014-03-06

申请号：US13717590

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Hyung Jin PARK

IPC: H01L27/08

CPC classification number: H01L21/76877 ,  H01L21/02282 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32115 ,  H01L21/76852 ,  H01L21/76897 ,  H01L27/08 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/40 ,  H01L28/90 ,  H01L29/4236

Abstract: A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented.

Abstract translation: 半导体器件包括形成在半导体衬底上的位线。 位线具有上部和下部，并且上部比下部窄。 在位线的侧壁上形成阻挡膜，并且通过填充位线之间的空间使得存储节点接触件的上部比存储节点接触件的下部更宽地获得存储节点接触插塞。 结果，可以简化该过程，并且可以防止存储节点接触插头和位线之间的短路。

公开(公告)号：US20240363548A1

公开(公告)日：2024-10-31

申请号：US18461503

申请日：2023-09-06

Applicant: SK hynix Inc.

Inventor： Geon Hee KIM ,  Hyung Jin PARK ,  Seung Won LEE

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5283

Abstract: A wafer includes chip areas and a first scribe lane disposed between the chip areas, and a first trench pattern disposed in the first scribe lane. The first scribe lane extends in a first direction. The first trench pattern includes a plurality of first trench groups spaced apart from each other in the first direction.

公开(公告)号：US20150072513A1

公开(公告)日：2015-03-12

申请号：US14539906

申请日：2014-11-12

Applicant: SK hynix Inc.

Inventor： Hyung Jin PARK

IPC: H01L21/768 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02282 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32115 ,  H01L21/76852 ,  H01L21/76897 ,  H01L27/08 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/40 ,  H01L28/90 ,  H01L29/4236

Abstract: A semiconductor device comprises a bit line formed over a semiconductor substrate. The bit line has an upper portion and a lower portion, and the upper portion is narrower than the lower portion. An barrier film is formed over sidewalls of the bit line, and a storage node contact plug is obtained by filling a space between the bit lines so that an upper portion of the storage node contact is wider than a lower portion of the storage node contact. As a result, the process can be simplified and a short between the storage node contact plug and the bit line can be prevented.

Abstract translation: 半导体器件包括形成在半导体衬底上的位线。 位线具有上部和下部，并且上部比下部窄。 在位线的侧壁上形成阻挡膜，并且通过填充位线之间的空间使得存储节点接触件的上部比存储节点接触件的下部更宽地获得存储节点接触插塞。 结果，可以简化该过程，并且可以防止存储节点接触插头和位线之间的短路。

公开(公告)号：US20220216162A1

公开(公告)日：2022-07-07

申请号：US17360847

申请日：2021-06-28

Applicant: SK hynix Inc.

Inventor： Hyung Jin PARK ,  Jung Wook KIM ,  Hyo Jun LEE

IPC: H01L23/544

Abstract: Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.