公开(公告)号：US20240363548A1

公开(公告)日：2024-10-31

申请号：US18461503

申请日：2023-09-06

申请人： SK hynix Inc.

发明人： Geon Hee KIM ,  Hyung Jin PARK ,  Seung Won LEE

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/562 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5283

摘要： A wafer includes chip areas and a first scribe lane disposed between the chip areas, and a first trench pattern disposed in the first scribe lane. The first scribe lane extends in a first direction. The first trench pattern includes a plurality of first trench groups spaced apart from each other in the first direction.

公开(公告)号：US20240006333A1

公开(公告)日：2024-01-04

申请号：US17986976

申请日：2022-11-15

申请人： SK hynix Inc.

发明人： Seung Won LEE ,  Hyung Jin PARK ,  Han Bit KIM ,  Jeong Woo HONG

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54426

摘要： A semiconductor includes an underlayer; a lower core layer spaced apart from the underlayer, the lower core layer including a plurality of lower segments spaced apart from each other in a horizontal direction; an upper core layer spaced apart from the lower core layer, the upper core layer including a plurality of upper segments spaced apart from each other in the horizontal direction; a post pattern vertically penetrating the upper core layer and the lower core layer; a passivation layer surrounding the lower core layer, the upper core layer, and the post pattern; coating layer surrounding the passivation layer; and a support pattern extending in the vertical direction and passing through the lower core layer, the upper core layer, the passivation layer, and the coating layer.

公开(公告)号：US20230005788A1

公开(公告)日：2023-01-05

申请号：US17544516

申请日：2021-12-07

申请人： SK hynix Inc.

发明人： Nam Yeal LEE ,  Seung Won LEE ,  Dong Sub KWAK

IPC分类号： H01L21/768 ,  H01L23/522

摘要： A method for fabricating a semiconductor device includes: forming a dielectric layer over a substrate; forming a hole-shaped partial via in the dielectric layer; forming a line-shaped trench that partially overlaps with the partial via and has a greater line width than a line width of the partial via in the dielectric layer; forming a hole-shaped via that has a smaller line width than the line width of the partial via and penetrates the dielectric layer on a lower surface of the partial via; and gap-filling the via, the partial via and the trench with a conductive material, wherein a lower surface of the trench is positioned at a higher level than the lower surface of the partial via.