公开(公告)号：US20150031180A1

公开(公告)日：2015-01-29

申请号：US14512091

申请日：2014-10-10

Applicant: SK hynix Inc.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Eun-Shil PARK

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/28026 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/7827

Abstract: A method for fabricating vertical channel transistors includes forming a plurality of pillars which have laterally opposing both sidewalls, over a substrate; forming a gate dielectric layer on both sidewalls of the pillars; forming first gate electrodes which cover any one sidewalls of the pillars and shield gate electrodes which cover the other sidewalls of the pillars and have a height lower than the first gate electrodes, over the gate dielectric layer; and forming second gate electrodes which are connected with upper portions of sidewalls of the first gate electrodes.

Abstract translation: 一种用于制造垂直沟道晶体管的方法，包括在衬底上形成横向相对的两个侧壁的多个柱; 在支柱的两个侧壁上形成栅介电层; 形成覆盖所述柱的任何一个侧壁的第一栅电极和覆盖所述柱的其它侧壁并且具有低于所述第一栅电极的高度的屏蔽栅电极; 以及形成与所述第一栅电极的侧壁的上部连接的第二栅电极。

公开(公告)号：US20140061850A1

公开(公告)日：2014-03-06

申请号：US13718683

申请日：2012-12-18

Applicant: SK HYNIX INC.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Eun-Shil PARK ,  Tae-Yoon KIM ,  Ju-Hyun MYUNG ,  Kyu-Hyung YOON

IPC: H01L27/02 ,  H01L21/762

CPC classification number: H01L27/0203 ,  H01L21/76229 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10885

Abstract: A method for fabricating a semiconductor device includes forming active regions which are separated by a plurality of first trenches, forming supports which fill the first trenches; etching the active regions and defining second trenches which are shallower than the first trenches, forming spacers on sidewalls of the second trenches, etching bottoms of the second trenches and defining third trenches, forming punch-through preventing patterns which fill lower portions of the third trenches, etching sidewalls which are not protected by the punch-through preventing patterns and the spacers, and forming recessed sidewalls which face each other, and forming buried bit lines in the recessed sidewalls.

Abstract translation: 一种制造半导体器件的方法，包括形成由多个第一沟槽分离的有源区，形成填充第一沟槽的支撑体; 蚀刻有源区并限定比第一沟槽浅的第二沟槽，在第二沟槽的侧壁上形成间隔物，蚀刻第二沟槽的底部并限定第三沟槽，形成填充第三沟槽的下部的穿通防止图案 蚀刻不被穿通防止图案和间隔物保护的侧壁，并且形成彼此面对的凹陷侧壁，并且在凹陷侧壁中形成掩埋位线。

公开(公告)号：US20140024214A1

公开(公告)日：2014-01-23

申请号：US13720059

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Tae-Yoon KIM ,  Heung-Jae CHO

IPC: H01L21/02

CPC classification number: H01L21/02697 ,  H01L21/743 ,  H01L27/10885

Abstract: A method for fabricating a semiconductor device including a semiconductor substrate having a trench formed therein. A migration assist layer is formed in the trench and on the substrate. A buried layer in formed in the trench by migrating material from the migration assist layer and the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法，该半导体器件包括其中形成沟槽的半导体衬底。 在沟槽和衬底上形成迁移辅助层。 通过从迁移辅助层和半导体衬底迁移材料而形成在沟槽中的掩埋层。

公开(公告)号：US20140061746A1

公开(公告)日：2014-03-06

申请号：US13720109

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Eun-Shil PARK

IPC: H01L27/06 ,  H01L21/8239

CPC classification number: H01L27/10885 ,  H01L21/8239 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract translation: 一种制造半导体器件的方法包括蚀刻半导体衬底以形成在半导体衬底中限定多个有源区的灯泡型沟槽; 在每个灯泡型沟槽中形成支撑件; 通过在每个有源区域形成沟槽，将多个有源区域中的每个有源区域划分成一对体线; 并且在一对身体线的每条体线中形成位线。

公开(公告)号：US20150091070A1

公开(公告)日：2015-04-02

申请号：US14565222

申请日：2014-12-09

Applicant: SK hynix Inc.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Eun-Shil PARK

IPC: H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10885 ,  H01L21/8239 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract translation: 一种制造半导体器件的方法包括蚀刻半导体衬底以形成在半导体衬底中限定多个有源区的灯泡型沟槽; 在每个灯泡型沟槽中形成支撑件; 通过在每个有源区域形成沟槽，将多个有源区域中的每个有源区域划分成一对体线; 并且在一对身体线的每条体线中形成位线。

公开(公告)号：US20140097519A1

公开(公告)日：2014-04-10

申请号：US13717512

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Tae-Yoon KIM ,  Kyu-Hyung YOON

IPC: H01L29/02 ,  H01L21/18

CPC classification number: H01L29/02 ,  H01L21/185 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891 ,  H01L28/40

Abstract: A method for fabricating a semiconductor device includes forming a first semiconductor wafer, in which a circuit part and a first bonding layer are stacked, on a first semiconductor substrate, forming a second semiconductor wafer, which includes structures and an insulating layer for gap-filling between the structures, on a second semiconductor substrate, the structures including a pillar and bit lines stacked therein, bonding the first semiconductor wafer with the second semiconductor wafer so that the first bonding layer faces the insulating layer, and separating the second semiconductor substrate from the bonded second semiconductor wafer.

Abstract translation: 一种制造半导体器件的方法包括在第一半导体衬底上形成第一半导体晶片，其中电路部分和第一接合层堆叠在其中，形成第二半导体晶片，其包括结构和用于间隙填充的绝缘层 在所述结构之间，在第二半导体衬底上，包括堆叠在其中的柱和位线的结构，将所述第一半导体晶片与所述第二半导体晶片接合，使得所述第一结合层面向所述绝缘层，以及将所述第二半导体衬底与所述第二半导体衬底分离 粘合的第二半导体晶片。

公开(公告)号：US20140021485A1

公开(公告)日：2014-01-23

申请号：US13711673

申请日：2012-12-12

Applicant: SK HYNIX INC.

Inventor： Heung-Jae CHO

IPC: H01L29/16 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L21/26506 ,  H01L27/10808 ,  H01L27/10873 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical channel transistor includes a pillar formed over a substrate, and a gate electrode formed on sidewalls of the pillar, wherein the pillar includes a source area, a vertical channel area over the source area, a drain area over the vertical channel area, and a leakage prevention area interposed between the vertical channel area and the drain area.

Abstract translation: 垂直沟道晶体管包括形成在衬底上的柱和形成在柱的侧壁上的栅电极，其中柱包括源区，源区上的垂直沟道区，垂直沟道区上的漏区，以及 设置在垂直沟道区域和漏极区域之间的防漏区域。

公开(公告)号：US20140011334A1

公开(公告)日：2014-01-09

申请号：US13716931

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Heung-Jae CHO ,  Tae-Yoon KIM

IPC: H01L29/66 ,  H01L21/8239

CPC classification number: H01L29/66666 ,  H01L21/8239 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor body lines in which a plurality of buried bit lines are buried, to be separated by a plurality of trenches, forming a filling layer that fills each of the plurality of trenches, forming a conductive layer over the plurality of semiconductor body lines and the filling layer, forming a plurality of semiconductor pillars over the plurality of semiconductor body lines by etching the conductive layer.

Abstract translation: 一种制造半导体器件的方法，包括：形成多个埋置位线的多个半导体本体线，被多个沟槽隔开，形成填充多个沟槽中的每一个的填充层，形成 在所述多个半导体体线和所述填充层上形成导电层，通过蚀刻所述导电层在所述多个半导体主体线上形成多个半导体柱。

公开(公告)号：US20130175603A1

公开(公告)日：2013-07-11

申请号：US13788319

申请日：2013-03-07

Applicant: SK hynix Inc.

Inventor： Heung-Jae CHO ,  Yong-Soo KIM ,  Beom-Yong KIM ,  Won-Joon CHOI ,  Jung-Ryul AHN

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing side walls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

Abstract translation: 一种用于制造垂直沟道型非易失性存储器件的方法包括：在半导体衬底上交替地形成多个牺牲层和多个层间电介质层; 蚀刻牺牲层和层间电介质层以形成多个用于通道的第一开口，每个开口暴露衬底; 填充第一开口以形成从半导体衬底突出的多个通道; 蚀刻牺牲层和层间电介质层以形成用于去除沟道之间的牺牲层的第二开口; 通过去除由第二开口暴露的牺牲层来暴露通道的侧壁; 以及在通道的暴露的侧壁上形成隧道绝缘层，电荷陷阱层，电荷阻挡层和用于栅电极的导电层。

公开(公告)号：US20160086957A1

公开(公告)日：2016-03-24

申请号：US14962933

申请日：2015-12-08

Applicant: SK hynix Inc.

Inventor： Heung-Jae CHO ,  Eui-Seong HWANG ,  Eun-Shil PARK

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L21/8239 ,  H01L27/0629 ,  H01L27/10814 ,  H01L27/10876 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating a semiconductor device includes etching semiconductor substrate to form bulb-type trenches that define a plurality of active regions in the semiconductor substrate; forming a supporter in each of the bulb-type trenches; dividing each active region, of the plurality of active regions, into a pair of body lines by forming a trench through each active region; and forming a bit line in each body line of the pair of body lines.

Abstract translation: 一种制造半导体器件的方法包括蚀刻半导体衬底以形成在半导体衬底中限定多个有源区的灯泡型沟槽; 在每个灯泡型沟槽中形成支撑件; 通过在每个有源区域形成沟槽，将多个有源区域中的每个有源区域划分成一对体线; 并且在一对身体线的每条体线中形成位线。