公开(公告)号：US20210313246A1

公开(公告)日：2021-10-07

申请号：US17062765

申请日：2020-10-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Toshiaki MATSUMURA ,  Nao NAGASE ,  Yoshihiko SAITO ,  Nobutoshi SUGAWARA ,  Takahiro TANAMACHI

IPC: H01L23/31 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/522 ,  H01L21/56

Abstract: Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.

公开(公告)号：US20230345720A1

公开(公告)日：2023-10-26

申请号：US17660278

申请日：2022-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nao NAGASE ,  Chiko KUDO ,  Tsutomu IMAI

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.

公开(公告)号：US20230345716A1

公开(公告)日：2023-10-26

申请号：US17660265

申请日：2022-04-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tsutomu IMAI ,  Nao NAGASE ,  Chiko KUDO ,  Sadao FUKUNO

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L27/11582 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A sacrificial memory opening fill structure for a multi-tier memory device may include a semiconductor fill material portion a metallic fill material portion to enhance control of a vertical cross-sectional profile of an inter-tier memory opening. Multiple inter-tier dielectric layers may be employed to reduce sharp corners in a memory opening fill structure. Alternatively or additionally, a combination of an isotropic etch process followed by an anisotropic etch process may be used to form a first-tier memory opening.