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1.发明授权公开(公告)号：US12224766B2
公开(公告)日：2025-02-11
申请号：US18057969
申请日：2022-11-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young Sea Cho , Wan Kim , Yong Lim
Abstract: An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.
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公开(公告)号：US20210067150A1
公开(公告)日：2021-03-04
申请号：US16855593
申请日：2020-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehoon Lee , Yong Lim , Wan Kim , Barosaim Sung , Seunghyun Oh
Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.
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公开(公告)号：US11611315B2
公开(公告)日：2023-03-21
申请号：US17173943
申请日：2021-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong Mi Lee , Yong Lim , Chilun Lo
Abstract: A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.
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公开(公告)号：US11509298B2
公开(公告)日：2022-11-22
申请号：US17514552
申请日：2021-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehoon Lee , Yong Lim , Wan Kim , Barosaim Sung , Seunghyun Oh
Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.
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公开(公告)号：US11018685B2
公开(公告)日：2021-05-25
申请号：US15931729
申请日：2020-05-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woo Jin Jang , Yong Lim , Seung Hyun Oh , Jae Hoon Lee
Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.
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Patent Agency Ranking
公开(公告)号：US09380233B2
公开(公告)日：2016-06-28
申请号：US14185081
申请日：2014-02-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han Yang , Kyoung Min Koh , Yong Lim , Shin Hoo Kim , Ju Ha Kim , Seung Jin Lee , Jae Jin Jung , Kee Moon Chun
IPC: H04N5/361
CPC classification number: H04N5/361
Abstract: An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.
Abstract translation: 图像传感器包括像素阵列，其包括至少一个有源像素和布置在包括第一至第n行和第一至第m列的矩阵中的至少一个线光学黑（L-OB）像素，所述像素阵列被配置为输出像素 在第一到第n行之一的读出操作期间以列为单位的信号和暗电平偏移信号; 行驱动器，被配置为向第一至第n行输出选择控制信号; 以及被配置为数字化像素信号和暗电平偏移信号的模数转换器（ADC）块。 在像素阵列中，在第一至第n行之一的读出操作期间，从另一行中的L-OB像素同时输出暗电平偏移信号。 这里，'n'和'm'分别表示等于或大于'2'的整数。
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公开(公告)号：US11984907B2
公开(公告)日：2024-05-14
申请号：US17564668
申请日：2021-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yong Lim , Jaehoon Lee
Abstract: An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.
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公开(公告)号：US11804848B2
公开(公告)日：2023-10-31
申请号：US17705776
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon Lee , Yong Lim , Seunghyun Oh
CPC classification number: H03M1/466 , H03K3/356104 , H03M1/1245 , H03M1/462
Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.
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公开(公告)号：US20210091782A1
公开(公告)日：2021-03-25
申请号：US15931729
申请日：2020-05-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woo Jin Jang , Yong Lim , Seung Hyun Oh , Jae Hoon Lee
Abstract: An analog-to-digital converter includes a comparator configured to compare an input signal with a reference signal and to output a comparison signal indicating a corresponding comparison result, a control logic configured to output a control signal for adjusting the reference signal based on the comparison signal, and a reference signal adjusting circuit configured to adjust the reference signal based on the control signal. The comparator includes a first pre-amplifier configured to amplify a difference between the input signal and the reference signal using a first transistor having a first size, a second pre-amplifier configured to amplify the difference between the input signal and the reference signal using a second transistor having a second size different from the first size, and a latch configured to generate the comparison signal using at least one of an output of the first and second pre-amplifiers. The first and second pre-amplifiers share the latch.
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公开(公告)号：US12191881B2
公开(公告)日：2025-01-07
申请号：US18150636
申请日：2023-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae Hoon Lee , Yong Lim
Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.
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