摘要:
An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.
摘要:
An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.
摘要:
An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.
摘要:
An image sensor includes a pixel array including at least one active pixel and at least one line-optical black (L-OB) pixel arranged in a matrix including first to nth rows and first to mth columns, the pixel array configured to output a pixel signal and a dark-level offset signal in units of columns during a read-out operation in one of the first to nth rows; a row driver configured to output a selection control signal to the first to nth rows; and an analog-to-digital converter (ADC) block configured to digitize the pixel signal and the dark-level offset signal. In the pixel array, a dark-level offset signal is simultaneously output from an L-OB pixel in another row during the read-out operation in one of the first to nth rows. Here, ‘n’ and ‘m’ each denote an integer that is equal to or greater than ‘2’.
摘要:
Provided are image sensors. An image sensor includes a pixel array comprising pixels configured to output signal voltages, each of the pixels comprising first and second photodiodes, first and second transfer transistors connected to the first and second photodiodes, respectively, and a floating diffusion node to which the first and second transfer transistors are connected; a ramp voltage generator configured to generate a ramp voltage that decreases with a slope according to a ramp clock to have a first gain; a correlation double sampler (CDS) configured to compare the ramp voltage with the signal voltages to output a comparison signal; a counter configured to count the comparison signal according to a counter clock to output a digital signal; and a digital scaling unit configured to scale the digital signal to have a second gain.
摘要:
The image sensor includes a plurality of column lines, a plurality of active road circuits and a selection circuit. The plurality of column lines are each connected to a corresponding one of a plurality of pixels. The plurality of active road circuits are each connected to a corresponding one of the plurality of column lines. The selection circuit is configured to enable a portion of the plurality of active road circuits based on a plurality of column selection signals.
摘要:
An image sensor chip includes an internal voltage generator for generating internal voltages using an external voltage received at a first terminal of the image sensor chip, a temperature sensor for generating a temperature voltage, a selection circuit for outputting one of the external voltage, the internal voltages, and the temperature voltage, a digital code generation circuit for generating a digital code using an output voltage of the selection circuit, and a second terminal for outputting the digital code from the image sensor chip.
摘要:
An image sensor is disclosed. The image sensor includes a plurality of pixels, a switch circuit coupled to the pixels and configured to substantially simultaneously output signals output only from pixels having similar characteristics among the pixels in response to a control signal; and a comparison circuit configured to convert the signals output from the switch circuit into digital signals. The pixels having similar characteristics are located across among the plurality of pixels.
摘要:
Provided are image sensors. An image sensor includes a pixel array comprising pixels configured to output signal voltages, each of the pixels comprising first and second photodiodes, first and second transfer transistors connected to the first and second photodiodes, respectively, and a floating diffusion node to which the first and second transfer transistors are connected; a ramp voltage generator configured to generate a ramp voltage that decreases with a slope according to a ramp clock to have a first gain; a correlation double sampler (CDS) configured to compare the ramp voltage with the signal voltages to output a comparison signal; a counter configured to count the comparison signal according to a counter clock to output a digital signal; and a digital scaling unit configured to scale the digital signal to have a second gain.
摘要:
An image sensor includes multiple counters and a counter controller. Each counter of the multiple counters is configured to perform counting of a comparison result signal and to generate a count result, the comparison result signal being obtained by comparing a ramp signal and a pixel signal of a column of multiple columns. The counter controller is configured to generate and transmit a counter clock signal and (n−1) delay clock signals to the counters, respectively, “n” being a natural number equal to or greater than two. Each delay clock signal of the (n−1) delay clock signals is obtained by delaying the counter clock signal by a corresponding offset code.