公开(公告)号：US20210111114A1

公开(公告)日：2021-04-15

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20210125908A1

公开(公告)日：2021-04-29

申请号：US16946209

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20240096777A1

公开(公告)日：2024-03-21

申请号：US18323646

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesun KIM ,  Sanghyun LEE ,  Yeonho JANG ,  Yunseok CHOI

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L22/12 ,  H01L22/14 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511

Abstract: A semiconductor package includes a redistribution structure in which redistribution layers and insulating layers are alternately stacked. A semiconductor chip is electrically connected to the redistribution layers, and bumps are electrically connected to the redistribution layers and arranged on one surface of the redistribution structure. The redistribution layers include pads arranged to face the bumps, and each of the pads includes a first pad portion offset from a center of each of the pads in a first direction, a second pad portion offset from the center of each of the pads in a second direction, and a connection portion connecting the first and second pad portions. The connection portion includes a protruding portion that defines a first recessed region recessed adjacent to the first pad portion and a second recessed region recessed adjacent to the second pad portion.

公开(公告)号：US20230148218A1

公开(公告)日：2023-05-11

申请号：US18153601

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Jongyoun KIM ,  Jungho PARK ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/49866 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/4853 ,  H01L2224/16227

Abstract: A semiconductor package includes a semiconductor chip; a redistribution insulating layer including a first opening; an external connection bump including a first part in the first opening; a lower bump pad including a first surface in physical contact with the first part of the external connection bump and a second surface opposite to the first surface, wherein the first surface and the redistribution insulating layer partially overlap; and a redistribution pattern that electrically connects the lower bump pad to the semiconductor chip.

公开(公告)号：US20230026972A1

公开(公告)日：2023-01-26

申请号：US17700818

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonho JANG ,  Dongkyu KIM ,  Shang-Hoon SEO ,  Jaegwon JANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L23/00

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package includes a lower structure and an upper redistribution layer. The lower structure includes a first bump layer, a lower redistribution layer, a semiconductor chip, a molding layer, a conductive pillar, and an under pad layer. The upper redistribution layer includes a second bump layer and second redistribution layers. The first redistribution layer includes a lower redistribution pattern including a first line part and a first via part. A width of the first via part increases in a direction toward the first line part from a bottom surface of the first via part. The second redistribution layer includes an upper redistribution pattern including a second line part and the second via part. A width of the second via part increases in a direction toward the second line part from a top surface of the second via part.

公开(公告)号：US20240096815A1

公开(公告)日：2024-03-21

申请号：US18244739

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon JANG ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/544 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/544 ,  H01L23/49822 ,  H01L25/105 ,  H01L25/16 ,  H01L24/48 ,  H01L2223/54426 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes: a first package substrate including a first redistribution structure; a second package substrate including a second redistribution structure; a semiconductor chip provided between the first package substrate and the second package substrate, and attached to the first package substrate; and a fiducial mark provided on the second package substrate and separated from the second redistribution structure in a plan view.

公开(公告)号：US20220406702A1

公开(公告)日：2022-12-22

申请号：US17892215

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.

公开(公告)号：US20200373243A1

公开(公告)日：2020-11-26

申请号：US16671625

申请日：2019-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon JANG ,  lnwon O ,  Jongyoun KIM ,  Seokhyun LEE ,  Yeonho JANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

公开(公告)号：US20250062208A1

公开(公告)日：2025-02-20

申请号：US18623645

申请日：2024-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  Kyung Don MUN ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package may include a first redistribution layer structure, a chiplet structure on the first redistribution layer structure, a plurality of first connection members on the first redistribution layer structure, a first molding material on the first redistribution layer structure and molding the chiplet structure and the plurality of first connection members, and a second redistribution layer structure on the first molding material. The chiplet structure may include a third redistribution layer structure, a first chiplet and a second chiplet on the third redistribution layer structure, and a bridge die on a bottom surface of the third redistribution layer structure.

公开(公告)号：US20240178122A1

公开(公告)日：2024-05-30

申请号：US18226352

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Sangjin BAEK ,  Kyoung Lim SUK ,  Shang-Hoon SEO ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.