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公开(公告)号:US20200075627A1
公开(公告)日:2020-03-05
申请号:US16294425
申请日:2019-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: SUNG-SOO AHN , YONG-HOON SON , MINHYUK KIM , JAE HO MIN , DAEHYUN JANG
IPC: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L21/28 , H01L21/311
Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.
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公开(公告)号:US20200119009A1
公开(公告)日:2020-04-16
申请号:US16716384
申请日:2019-12-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YOONJAE KIM , CHEOL KIM , YONG-HOON SON , JIN-HYUK YOO , WOOJIN JUNG
IPC: H01L27/088 , H01L29/78 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/08 , H01L29/06 , H01L27/02 , H01L21/8234 , H01L21/311 , H01L21/306 , H01L21/768 , H01L23/485
Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
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公开(公告)号:US20210257370A1
公开(公告)日:2021-08-19
申请号:US17036462
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: YONG-HOON SON
IPC: H01L27/108 , G11C7/18
Abstract: Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.
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公开(公告)号:US20210104527A1
公开(公告)日:2021-04-08
申请号:US17035843
申请日:2020-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: YONG-HOON SON
IPC: H01L27/108 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.
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公开(公告)号:US20220285356A1
公开(公告)日:2022-09-08
申请号:US17752921
申请日:2022-05-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: YONG-HOON SON
IPC: H01L27/108 , H01L29/66 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/06
Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.
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公开(公告)号:US20170317079A1
公开(公告)日:2017-11-02
申请号:US15413466
申请日:2017-01-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: YOONJAE KIM , CHEOL KIM , YONG-HOON SON , JIN-HYUK YOO , WOOJIN JUNG
IPC: H01L27/088 , H01L21/306 , H01L29/66 , H01L29/423 , H01L29/165 , H01L29/10 , H01L29/08 , H01L29/06 , H01L27/02 , H01L21/8234 , H01L21/311 , H01L29/78
Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.
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