公开(公告)号：US20180197732A1

公开(公告)日：2018-07-12

申请号：US15910583

申请日：2018-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-IK OH ,  DAEHYUN JANG ,  HA-NA KIM ,  KYOUNGSUB SHIN

IPC: H01L21/027 ,  H01L27/11575 ,  H01L21/308 ,  H01L27/11556 ,  H01L21/306 ,  H01L27/11582 ,  H01L27/24 ,  H01L25/00 ,  H01L27/11521 ,  H01L25/065 ,  H01L45/00

CPC classification number: H01L21/0274 ,  H01L21/30604 ,  H01L21/3085 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

公开(公告)号：US20160372322A1

公开(公告)日：2016-12-22

申请号：US15249903

申请日：2016-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-IK OH ,  DAEHYUN JANG ,  HA-NA KIM ,  KYOUNGSUB SHIN

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/306 ,  H01L27/115 ,  H01L27/24

CPC classification number: H01L21/0274 ,  H01L21/30604 ,  H01L21/3085 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2481 ,  H01L45/122 ,  H01L45/1253 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.

Abstract translation: 提供了三维半导体器件的阶梯状连接结构。 该装置包括在基板上的电极结构，电极结构包括上层阶段区域，下层阶梯区域和它们之间的缓冲区域。 电极结构包括依次堆叠在基板上的水平电极，水平电极包括构成上下阶梯区域中的每一个的阶梯结构的多个焊盘区域，并且缓冲区域的宽度大于 垫区域。

公开(公告)号：US20200075627A1

公开(公告)日：2020-03-05

申请号：US16294425

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNG-SOO AHN ,  YONG-HOON SON ,  MINHYUK KIM ,  JAE HO MIN ,  DAEHYUN JANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/28 ,  H01L21/311

Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.