公开(公告)号：US20240304704A1

公开(公告)日：2024-09-12

申请号：US18592697

申请日：2024-03-01

申请人： Samsung Electronics Co., Ltd.

发明人： Subin Lee ,  Hyunjun Lim ,  Jeonghyeon Lee ,  Hakjong Lee ,  Taeho Cha ,  Seunghyeon Hong

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66545 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： Provided is an integrated circuit device including a plurality of fin-type active areas each extending on a substrate in a first horizontal direction, a plurality of gate structures each extending in a second horizontal direction intersecting the plurality of fin-type active areas on the substrate and spaced apart from each other in the first horizontal direction, an interlayer insulating layer covering the periphery of the plurality of gate structures, and an inter-gate cutting layer formed of an insulating material and extending in the first horizontal direction across through the plurality of gate structures and the interlayer insulating layer. A first gate structure is separated from a second gate structure by the inter-gate cutting layer, and portions of respective side surfaces of the gate structures overlap the plurality of fin-type active areas in a vertical direction, the respective side surfaces of the gate structures extending in the first horizontal direction.

公开(公告)号：US20240321874A1

公开(公告)日：2024-09-26

申请号：US18499117

申请日：2023-10-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonghyeon Lee ,  Hakjong Lee ,  Yeonghan Gwon ,  Hanyoung Song ,  Subin Lee ,  Junyoup Lee ,  Hyunjun Lim ,  Taeho Cha ,  Seunghyeon Hong

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/823481

摘要： An integrated circuit device includes a pair of fin-type active regions collinear with each other on a substrate, a gate line disposed on one of the fin-type active regions, a capping insulating layer that covers the gate line, and a fin isolation insulating portion that passes through the capping insulating layer in a vertical direction between the pair of fin-type active regions. The fin isolation insulating portion includes an isolation insulating plug that includes a first portion disposed between the pair of fin-type active regions and a second portion integrally connected to the first portion and that passes through the capping insulating layer in the vertical direction, and an isolation insulating liner that surrounds a bottom surface and a sidewall of the isolation insulating plug. The isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surface of the isolation insulating plug.