公开(公告)号：US20240371762A1

公开(公告)日：2024-11-07

申请号：US18434391

申请日：2024-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosung Park ,  Jiwon Park ,  Minseok Jo ,  Junyoup Lee ,  Jinyoung Choi

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An example semiconductor device includes an active region extending in a first direction and including first conductivity-type impurities, an ion doped region extending in the first direction in the active region and including second conductivity-type impurities, a gate structure extending in a second direction, intersecting the first direction, disposed on the active region and traversing the active region, a source/drain region on the active region on at least one side of the gate structure, a device isolation layer surrounding the active region, an interlayer insulating layer on the device isolation layer and covering the gate structure and the source/drain region, a vertical power structure extending in a third direction, perpendicular to the first and second directions, and passing through the device isolation layer and the interlayer insulating layer, and a bottom wiring connected to the vertical power structure and contacting a bottom surface of the active region.

公开(公告)号：US20240321874A1

公开(公告)日：2024-09-26

申请号：US18499117

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyeon Lee ,  Hakjong Lee ,  Yeonghan Gwon ,  Hanyoung Song ,  Subin Lee ,  Junyoup Lee ,  Hyunjun Lim ,  Taeho Cha ,  Seunghyeon Hong

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76224 ,  H01L21/823481

Abstract: An integrated circuit device includes a pair of fin-type active regions collinear with each other on a substrate, a gate line disposed on one of the fin-type active regions, a capping insulating layer that covers the gate line, and a fin isolation insulating portion that passes through the capping insulating layer in a vertical direction between the pair of fin-type active regions. The fin isolation insulating portion includes an isolation insulating plug that includes a first portion disposed between the pair of fin-type active regions and a second portion integrally connected to the first portion and that passes through the capping insulating layer in the vertical direction, and an isolation insulating liner that surrounds a bottom surface and a sidewall of the isolation insulating plug. The isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surface of the isolation insulating plug.