公开(公告)号：US09190272B1

公开(公告)日：2015-11-17

申请号：US14331715

申请日：2014-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： CheolWoo Park ,  Kwangyul Lee ,  Jeongeon Lee ,  Seokjun Won ,  HyungSuk Jung

IPC: H01L21/033 ,  H01L29/51 ,  H01L27/088 ,  H01L29/49 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02063 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

Abstract: Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括：衬底，包括第一区域和第二区域，第一区域上的第一栅极图案，第二区域上的第二栅极图案，以及包围第一和第二栅极图案的层间绝缘层。 第一栅极图案包括第一栅极绝缘层和第一栅极电极，第二栅极图案包括第二栅极绝缘层和第二栅极电极，第一栅极绝缘层比第二栅极绝缘层厚，顶部宽度 的第二栅极图案大于其底部宽度。

公开(公告)号：US20130299916A1

公开(公告)日：2013-11-14

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L27/088

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

公开(公告)号：US20230194456A1

公开(公告)日：2023-06-22

申请号：US17935131

申请日：2022-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunho Kim ,  Jinhyeok Jang ,  Hyunwoo Kim ,  Jaeeun Song ,  Seokjun Won ,  Yigil Cho

IPC: G01N27/30 ,  G01N27/416 ,  G01N27/49

CPC classification number: G01N27/301 ,  G01N27/4161 ,  G01N27/49

Abstract: A filter contamination measuring device includes: a working electrode adjacent to a first surface of a filter, the filter configured to adsorb an ionic material of a first polarity, a counter electrode disposed on the other surface of the filter, a potentiostat configured to apply a voltage of a second polarity to the working electrode for a predetermined period of time, and to measure current output from the working electrode. The potentiostat is configured to increase the voltage over the predetermined amount of time. The filter contamination measuring device further includes a controller configured to calculate a maximum current attained during the predetermined amount of time and a corresponding voltage value, and to determine the type and concentration of the ionic material based on the maximum current and the voltage value.

公开(公告)号：US20230226560A1

公开(公告)日：2023-07-20

申请号：US17987179

申请日：2022-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yunho Kim ,  Jaeeun Song ,  Hyunwoo Kim ,  Seokjun Won ,  Taewan Kim ,  Jinhyeok Jang ,  Chungkyung Jung ,  Yigil Cho

IPC: B03C5/02 ,  C02F1/48 ,  C02F1/00

CPC classification number: B03C5/02 ,  C02F1/001 ,  C02F1/48 ,  B03C2201/24 ,  C02F2103/04

Abstract: An electrostatic purification device includes a purification tank housing configured to accommodate a fluid, a first electrode and a second electrode provided in the purification tank housing, a direct current (DC) power supply configured to apply a DC to the first electrode and the second electrode, a controller configured to monitor a current density between the first electrode and the second electrode, and determine whether purification is completed based on the current density, a first valve configured to control an introduction flow of the fluid into the purification tank housing, a second valve configured to control a discharge flow of the fluid from the purification tank housing, and a heat exchanger configured to cool the fluid accommodated in the purification tank housing.

公开(公告)号：US09525042B2

公开(公告)日：2016-12-20

申请号：US14700346

申请日：2015-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/28 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

公开(公告)号：US09064723B2

公开(公告)日：2015-06-23

申请号：US13751731

申请日：2013-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

IPC: H01L29/788 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。