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15 条记录 (耗时 0.018 秒)

    Method and apparatus for performing data recovery in a raid storage
    2.
    发明授权
    Method and apparatus for performing data recovery in a raid storage 有权

    公开(公告)号：US10467094B2

    公开(公告)日：2019-11-05

    申请号：US15429486

    申请日：2017-02-10

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sangwoo Kim ,  Jungho Yun

    IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/14 ,  G11C29/52 ,  G11C29/02 ,  G11C29/00 ,  G11C29/04

    摘要： A recovery method and apparatus for use in a redundant array of independent disks (RAID) storage device is provided that includes a plurality of nonvolatile memory devices. The recovery method includes: reading a data chunk, in which an uncorrectable error occurs, from the plurality of nonvolatile memory devices, selecting a plurality of sub-stripes including a parity and excluding the data chunk, and performing, in parallel, a first recovery operation of adjusting a read level to recover the data chunk and a second recovery operation of processing the plurality of sub-stripes to recover a sub-stripe including the data chunk. The parallel performance of the first and second recovery operations is completed according to an earlier completion of one of the first and second recovery operations.

    Power gating control circuit for stably controlling data restoring
    5.
    发明授权
    Power gating control circuit for stably controlling data restoring 有权

    公开(公告)号：US09941863B2

    公开(公告)日：2018-04-10

    申请号：US15090896

    申请日：2016-04-05

    申请人： Samsung Electronics Co., Ltd.

    发明人： Sangwoo Kim

    IPC分类号： H03K3/012 ,  H03K3/037

    CPC分类号： H03K3/012 ,  H03K3/0375

    摘要： Provided is a power gating control circuit for stably controlling data restoring. The power gating control circuit includes a retention circuit and a non-retention circuit. The retention circuit includes a first flip-flop, which stores or restores data of the first flip-flop in a power gating mode. The non-retention circuit includes a second flip-flop and a third flip-flop. The power gating control circuit performs initialization of data of the second flip-flop and the third flip-flop in the power gating mode, and an initialization operation of the non-retention circuit is controlled to be performed before data of the retention circuit is restored.

    IMAGE SENSOR DEVICE AND OPERATION METHOD THEREOF
    7.
    发明公开
    IMAGE SENSOR DEVICE AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240340549A1

    公开(公告)日：2024-10-10

    申请号：US18523624

    申请日：2023-11-29

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sangwoo Kim ,  Moo Young Kim ,  Yunhong Kim ,  Hyunjong Kim ,  Chanmin Park ,  Mira Lee

    IPC分类号： H04N25/709 ,  H04N25/76

    CPC分类号： H04N25/709 ,  H04N25/76

    摘要： Disclosed is an image sensor device which includes a pixel that outputs a first pixel signal to a first column line during a first time period and outputs a second pixel signal to the first column line during a second time period, and a clamp circuit that outputs a first clamp signal to the first column line during the first time period. During the first time period, a voltage of the first column line is determined based on the first pixel signal and the first clamp signal. The pixel operates based on a first power supply voltage, and the clamp circuit operates based on a second power supply voltage lower than the first power supply voltage.

    Apparatus, memory device, and method reducing clock training time
    8.
    发明授权
    Apparatus, memory device, and method reducing clock training time 有权

    公开(公告)号：US11923042B2

    公开(公告)日：2024-03-05

    申请号：US17581445

    申请日：2022-01-21

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sangwoo Kim ,  Younghoon Son ,  Seongheon Yu ,  Joungyeal Kim ,  Chulung Kim

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C29/12 ,  G11C29/46

    CPC分类号： G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12015 ,  G11C29/46

    摘要： An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.