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公开(公告)号：US20150372229A1
公开(公告)日：2015-12-24
申请号：US14609452
申请日：2015-01-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： MASAYUKI TERAI , IN-GYU BAEK
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146
Abstract: A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
Abstract translation: 电阻式存储器件包括设置在下布线上的开关器件，设置在开关器件上的电阻器元件和设置在电阻器元件上的上部互连件。 开关装置包括二极管电极，设置在二极管电极上的高浓度下阳极，设置在下部高浓度阳极电极上的中等浓度下阳极，设置在中浓度下阳极上的公共阴极，低 - 设置在公共阴极上的浓缩上阳极和设置在低浓度上阳极上的高浓度上阳极。 中等浓度下阳极的峰值掺杂浓度比低浓度上阳极的峰值掺杂浓度高至少10倍。
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公开(公告)号：US20220013171A1
公开(公告)日：2022-01-13
申请号：US17361534
申请日：2021-06-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MASAYUKI TERAI
Abstract: A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.
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Patent Agency Ranking
公开(公告)号：US20200111835A1
公开(公告)日：2020-04-09
申请号：US16394139
申请日：2019-04-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNGHYUN CHO , YOU-JIN JUNG , MASAYUKI TERAI , JINCHAN YUN
Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.
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公开(公告)号：US20190245142A1
公开(公告)日：2019-08-08
申请号：US16385052
申请日：2019-04-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MASAYUKI TERAI
CPC classification number: H01L45/124 , C23C16/34 , H01L21/02414 , H01L21/02417 , H01L21/02483 , H01L27/2409 , H01L27/2427 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1666 , H01L45/1675 , H01L45/1683 , H01L45/1691
Abstract: A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.
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公开(公告)号：US20180151623A1
公开(公告)日：2018-05-31
申请号：US15663065
申请日：2017-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MASAYUKI TERAI
CPC classification number: H01L27/2409 , C23C16/34 , H01L27/2427 , H01L27/2472 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: A memory cell pillar of a memory device includes a heating electrode having a base portion (leg) and a fin portion (ascender), and a selection device between a first conductive line and the heating electrode. A side surface of the selection device and a side surface of the fin portion extend along a first straight line. A method of fabricating a memory device includes forming a plurality of first insulating walls through a stack structure including a preliminary selection device layer and a preliminary electrode layer, forming a plurality of self-aligned preliminary heating electrode layers, forming a plurality of second insulating walls each between two of the plurality of first insulating walls, and forming a plurality of third insulating walls in a plurality of holes extending along a direction intersecting the plurality of first insulating walls.
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公开(公告)号：US20170117327A1
公开(公告)日：2017-04-27
申请号：US15188018
申请日：2016-06-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： MASAYUKI TERAI
IPC: H01L27/24 , H01L23/522 , H01L45/00
Abstract: A semiconductor device includes a first word line and a second word line extending abreast of each other in a first direction. A bit line extends between the first word line and the second word line in a second direction intersecting the first direction. A lower electrode is formed on one surface of the first word line. An ovonic threshold switch (OTS) is formed on the lower electrode. An intermediate electrode is formed on the OTS. A phase change memory (PCM) is formed on the intermediate electrode, and an upper electrode is formed between the first PCM and a surface of the bit line. The width of the first upper electrode in the second direction is narrower than the width of the first intermediate electrode in the second direction.
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公开(公告)号：US20150102282A1
公开(公告)日：2015-04-16
申请号：US14506005
申请日：2014-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： LIJIE ZHANG , YOUNG-BAE KIM , YOUN-SEON KANG , IN-GYU BAEK , MASAYUKI TERAI
CPC classification number: H01L27/249 , H01L27/2454 , H01L45/04 , H01L45/1226 , H01L45/146
Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.
Abstract translation: 半导体存储器件包括在垂直于衬底的方向上在衬底上直立延伸的柱，设置在衬底上并由第一层间绝缘层，第一导电层，第二层间绝缘层和第二导电层 插入在所述柱和所述第一导电层之间的可变电阻层以及插在所述第一柱和所述第二导电层之间的绝缘层。
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