公开(公告)号：US20210375922A1

公开(公告)日：2021-12-02

申请号：US17398455

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won PARK ,  Kyeong Jin PARK

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L23/48 ,  H01L21/28

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US20200098786A1

公开(公告)日：2020-03-26

申请号：US16378625

申请日：2019-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo Won PARK ,  Kyeong Jin PARK

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28 ,  H01L23/48

Abstract: A vertical-type memory device includes a plurality of gate electrode layers spaced apart from one another and stacked on a substrate, and extending by different lengths in a first direction and forming a staircase structure, a first interlayer insulating layer covering the staircase structure of the plurality of gate electrode layers, and a plurality of gate contact plugs penetrating the interlayer insulating layer and respectively in contact with the gate electrode layers. The plurality of gate electrode layers include lower gate electrode layers disposed adjacently to the substrate, and upper gate electrode layers disposed on the lower gate electrode layers, so that the lower gate electrodes are between the substrate and the upper gate electrode layers. The plurality of gate contact plugs include lower gate contact plugs connected to the lower gate electrode layers, and upper gate contact plugs connected to the upper gate electrode layers. The upper gate contact plugs have top-most portions disposed at a height higher than a height of top surfaces of the lower gate contact plugs.

公开(公告)号：US20190312051A1

公开(公告)日：2019-10-10

申请号：US16193283

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeong Jin PARK ,  Seo-Goo KANG ,  Kwonsoon JO ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/48 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11568

Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.

公开(公告)号：US20200176470A1

公开(公告)日：2020-06-04

申请号：US16780999

申请日：2020-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Mo GU ,  Kyeong Jin PARK ,  Hyun Mog PARK ,  Byoung II LEE ,  Tak LEE ,  Jun Ho CHA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11575

Abstract: A semiconductor device includes first gate electrodes including a first lower electrode, a first upper electrode disposed above the first lower electrode and including a first pad region, and one or more first intermediate electrodes disposed between the first lower electrode and the first upper electrode. Second gate electrodes include a second lower electrode, a second upper electrode disposed above the second lower electrode, and one or more second intermediate electrodes disposed between the second lower electrode and the second upper electrode. The second gate electrodes are sequentially stacked above the first upper electrode, while exposing the first pad region. The first lower electrode extends by a first length, further than the first upper electrode, in a first direction. The second lower electrode extends by a second length, different from the first length, further than the second upper electrode, in the first direction.

公开(公告)号：US20190267333A1

公开(公告)日：2019-08-29

申请号：US16106112

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Jun HONG ,  Kyeong Jin PARK

IPC: H01L23/58 ,  H01L27/12 ,  H01L27/115

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a cell array region including stacked structures and a word line cut region that extends between the stacked structures. Moreover, the semiconductor memory device includes a peripheral circuit region in a stack with the cell array region and including a support pattern.