公开(公告)号：US20190312051A1

公开(公告)日：2019-10-10

申请号：US16193283

申请日：2018-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeong Jin PARK ,  Seo-Goo KANG ,  Kwonsoon JO ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/48 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11568

Abstract: Disclosed is a semiconductor memory device comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.