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公开(公告)号：US20220293622A1
公开(公告)日：2022-09-15
申请号：US17668824
申请日：2022-02-10
发明人： Choasub KIM , Bongtae PARK , Jae-Joo SHIM , Sungil CHO
IPC分类号： H01L27/11565 , H01L23/535 , H01L27/11519 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
摘要： A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.
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2.发明公开公开(公告)号：US20240090211A1
公开(公告)日：2024-03-14
申请号：US18135349
申请日：2023-04-17
发明人： Soyeon KIM , Sung-Min HWANG , Dong-Sik LEE , Seunghyun CHO , Bongtae PARK , Jae-Joo SHIM
CPC分类号： H10B41/27 , H01L23/5283 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
摘要： A semiconductor memory device includes a gate stack structure including insulating layers, a lower selection line and word lines, the word lines including a first word line adjacent to the lower selection line and a second word line on the first word line, a memory channel structure penetrating the gate stack structure, a plurality of first contact plugs electrically connected to the first word line, a plurality of second contact plugs electrically connected to the second word line, a first conductive line connected to the plurality of first contact plugs, and a second conductive line connected to one of the plurality of second contact plugs.
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公开(公告)号：US20230094302A1
公开(公告)日：2023-03-30
申请号：US17747412
申请日：2022-05-18
发明人： Sung-Min HWANG , Dongsung WOO , Tae Gon LEE , Bongtae PARK , Jae-Joo SHIM , Tae-Chul JUNG
IPC分类号： H01L27/11526 , H01L27/11556 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L27/11573
摘要： A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.
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4.发明申请公开(公告)号：US20230005942A1
公开(公告)日：2023-01-05
申请号：US17678473
申请日：2022-02-23
发明人： Sung-Min HWANG , Jae-Joo SHIM , Dong-Sik LEE , Bongtae PARK
IPC分类号： H01L27/11539 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L27/11582 , H01L23/522 , H01L23/528
摘要： A 3D semiconductor memory device includes a substrate, a stack structure comprising interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate, vertical channel structures penetrating the stack structure, a separation structure spaced apart from the vertical channel structures and filling a trench crossing the stack structure, the separation structure comprising a spacer covering an inner sidewall of the trench, and a first conductive contact filling an inner space of the trench surrounded by the spacer, an insulating layer covering the substrate and the stack structure, contact plugs penetrating the insulating layer so as to be connected to the gate electrodes of the stack structure, and a second conductive contact spaced apart from the stack structure and penetrating the insulating layer so as to be connected to a peripheral circuit transistor. A bottom surface of the first conductive contact is at a level lower than a bottom surface of the spacer.
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公开(公告)号：US20210225868A1
公开(公告)日：2021-07-22
申请号：US17009075
申请日：2020-09-01
发明人： Kyungeun PARK , Jae-Joo SHIM , Dongsung WOO , Jongkwang LIM , Jaehoon JANG
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11565 , H01L27/11519 , H01L27/11539 , G11C7/18
摘要： Disclosed is a three-dimensional semiconductor memory device comprising a substrate including a cell region and a connection region, a plurality of inter-electrode dielectric layers and a plurality of electrode layers alternately stacked on the substrate, wherein ends of the plurality of electrode layers form a stepwise shape on the connection region, a planarized dielectric layer on the connection region and covering the ends of the plurality of electrode layers, and a first abnormal dummy vertical pattern on the connection region and penetrating the planarized dielectric layer in a first direction perpendicular to a top surface of the substrate. At least one of the plurality of electrode layers is positioned between the first abnormal dummy vertical pattern and the substrate and is insulated from the first abnormal dummy vertical pattern.
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公开(公告)号：US20140048873A1
公开(公告)日：2014-02-20
申请号：US14057094
申请日：2013-10-18
发明人： Jae-Joo SHIM , Han-Soo KIM , Won-Seok CHO , Jae-Hoon JANG , Sang-Yong PARK
IPC分类号： H01L29/78
CPC分类号： H01L29/7831 , H01L27/11582 , H01L29/7926
摘要： A semiconductor device includes a semiconductor pattern on a substrate, gate structures on sidewalls of the semiconductor pattern, the gate structures being spaced apart from one another, insulating interlayers among the gate structures, wherein an uppermost insulating interlayer is lower than an upper face of the semiconductor pattern, a common source line contacting the substrate and protruding above the uppermost insulating interlayer, an etch stop layer pattern on the semiconductor pattern and on the common source line wherein the common source line protrudes above the uppermost insulating interlayer, an additional insulating interlayer on the uppermost insulating interlayer, and contact plugs extending through the additional insulating interlayer so as to make contact with the semiconductor pattern and the common source line, respectively.
摘要翻译： 半导体器件包括衬底上的半导体图案，半导体图案的侧壁上的栅极结构，栅极结构彼此间隔开，栅极结构之间的绝缘夹层，其中最上层的绝缘中间层低于栅极结构的上表面 半导体图案，与基板接触并突出在最上层绝缘夹层之上的公共源极线，在半导体图案上的公共源极线上的共同源极线上的蚀刻停止层图案，其中共同源极线突出在最上面的绝缘中间层之上，在 最上层的绝缘中间层和延伸穿过附加绝缘夹层的接触插塞分别与半导体图案和公共源极线接触。
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