公开(公告)号：US20160133312A1

公开(公告)日：2016-05-12

申请号：US14790451

申请日：2015-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-SUK LEE ,  KYO-MIN SOHN ,  HO-YOUNG SONG ,  SANG-HOON SHIN ,  HAN-VIT JUNG

IPC: G11C11/4093 ,  G11C11/4096 ,  H01L25/065 ,  G11C11/4094

CPC classification number: H01L25/0657 ,  G11C7/1066 ,  G11C7/1069 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N−1).

Abstract translation: 一种包括堆叠半导体器件的存储器件，包括： 垂直堆叠在下基板上的上基板，上基板包括N个上穿通硅通孔（UTSV）和上驱动电路，下基板包括N个下穿通硅通孔（LTSV）和下驱动电路，其中每个 的上驱动电路在第K个UTSV和第（K + 1）个LTSV之间错开连接，其中'N'是大于1的自然数，'K'是从1到（N- 1）。

公开(公告)号：US20170352392A1

公开(公告)日：2017-12-07

申请号：US15479971

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-SUK LEE ,  REUM OH ,  JIN-SEONG PARK ,  SEUNG-HAN WOO

IPC: G11C7/22 ,  H03K19/21 ,  H03K3/356 ,  G11C5/06 ,  G11C5/02 ,  G11C7/12 ,  G11C7/10 ,  G11C7/06 ,  H04L7/033 ,  H01L25/065

CPC classification number: G11C7/222 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C5/063 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06544 ,  H03K3/356104 ,  H03K3/356156 ,  H03K19/21 ,  H04L7/033

Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a vertical direction, first and second signal paths, a transmission unit and a reception unit. The first and second signal paths electrically connect the plurality of semiconductor dies, where each of the first signal path and the second signal path includes at least one through-substrate via. The transmission unit generates a first driving signal and a second driving signal in synchronization with transitioning timing of a transmission signal to output the first driving signal to the first signal path and output the second driving signal to the second signal path. The reception unit receives a first attenuated signal corresponding to the first driving signal from the first signal path and receives a second attenuated signal corresponding to the second driving signal from the second signal path to generate a reception signal corresponding to the transmission signal.