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    Wafer bonding of micro-electro mechanical systems to active circuitry
    1.
    发明申请
    Wafer bonding of micro-electro mechanical systems to active circuitry 有权
    将微电子机械系统的晶片接合到有源电路

    公开(公告)号：US20060128058A1

    公开(公告)日：2006-06-15

    申请号：US11012589

    申请日：2004-12-15

    Applicant: Thomas Dungan ,  Ronald Fazzio

    Inventor： Thomas Dungan ,  Ronald Fazzio

    IPC: H01L21/50

    CPC classification number: B81C1/0023 ,  B81C2203/0118 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    Abstract: A single integrated wafer package includes a micro electromechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active device circuit on its first surface. The seal ring is adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component. An external contact is provided on the wafer package. The external contact is accessible externally to the wafer package and is electrically coupled to the active device circuit of the active device wafer.

    Abstract translation: 单个集成晶片封装包括微机电系统（MEMS）晶片，有源器件晶片和密封环。 MEMS晶片具有第一表面并且在其第一表面上包括至少一个MEMS部件。 有源器件晶片具有第一表面并且在其第一表面上包括有源器件电路。 密封环与MEMS晶片的第一表面相邻，使得围绕MEMS部件形成密封。 在晶片封装上提供外部触点。 外部触点可以在晶片封装外部访问，并且电耦合到有源器件晶片的有源器件电路。

    Integration of micro-electro mechanical systems and active circuitry
    2.
    发明申请
    Integration of micro-electro mechanical systems and active circuitry 审中-公开
    集成微机电系统和有源电路

    公开(公告)号：US20060125084A1

    公开(公告)日：2006-06-15

    申请号：US11012574

    申请日：2004-12-15

    Applicant: Ronald Fazzio ,  Thomas Dungan

    Inventor： Ronald Fazzio ,  Thomas Dungan

    IPC: H01L21/50 ,  H01L23/12

    CPC classification number: B81C1/00238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A single integrated wafer package includes a micro-electro mechanical system (MEMS) wafer, an active device wafer, and a seal ring. The MEMS wafer has a first surface and includes at least one MEMS component on its first surface. The active device wafer has a first surface and includes an active device circuit on its first surface. The seal ring is adjacent the first surface of the MEMS wafer such that a seal is formed about the MEMS component. An external contact is provided on the wafer package. The external contact is accessible externally to the wafer package and is electrically coupled to the MEMS device or active device circuit of the active device wafer.

    Abstract translation: 单个集成晶片封装包括微机电系统（MEMS）晶片，有源器件晶片和密封环。 MEMS晶片具有第一表面并且在其第一表面上包括至少一个MEMS部件。 有源器件晶片具有第一表面并且在其第一表面上包括有源器件电路。 密封环与MEMS晶片的第一表面相邻，使得围绕MEMS部件形成密封。 在晶片封装上提供外部触点。 外部接触件可从晶片封装的外部访问并且电耦合到有源器件晶片的MEMS器件或有源器件电路。

    Optical enhancement of integrated circuit photodetectors
    3.
    发明申请
    Optical enhancement of integrated circuit photodetectors 有权
    集成电路光电探测器的光学增强

    公开(公告)号：US20060097244A1

    公开(公告)日：2006-05-11

    申请号：US10984670

    申请日：2004-11-09

    Applicant: Chintamani Palsule ,  John Stanback ,  Thomas Dungan ,  Mark Crook

    Inventor： Chintamani Palsule ,  John Stanback ,  Thomas Dungan ,  Mark Crook

    IPC: H01L31/109

    CPC classification number: H01L27/1462 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14685

    Abstract: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable though the cover dielectric layer; and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device.

    Abstract translation: 一种半导体集成电路结构及其制造方法。 半导体集成电路结构包括与半导体衬底整体的光敏器件，设置在光敏器件上的覆盖电介质层，以及设置在覆盖电介质层上的透镜形成电介质层。 光通过覆盖电介质层可传输; 并透过透镜形成电介质层。 透镜形成电介质层形成嵌入的凸形微透镜。 微透镜将光引导到光敏设备上。

    Distributed silicon controlled rectifiers for ESD protection
    4.
    发明授权
    Distributed silicon controlled rectifiers for ESD protection 失效
    用于ESD保护的分布式可控硅整流器

    公开(公告)号：US5532896A

    公开(公告)日：1996-07-02

    申请号：US234882

    申请日：1994-04-26

    Applicant: Eugene Coussens ,  Thomas Dungan

    Inventor： Eugene Coussens ,  Thomas Dungan

    IPC: H02H9/04

    CPC classification number: H02H9/046

    Abstract: An electrostatic discharge (ESD) protection circuit for integrated circuitry having a switching ground bus for isolating switching noise includes an ESD protection bus. A first transistor pair includes a PNP transistor and an NPN transistor, with each of the transistors having an emitter connected to a signal input/output pad. A second transistor pair has a PNP transistor and an NPN transistor having emitters connected to the switching ground bus. For each of the PNP transistors, the base is connected to the ESD protection bus and the collector is connected to a "clean" ground bus. For each of the NPN transistors, a base is connected to the clean ground bus and a collector is connected to the ESD protection bus. In this configuration, the PNP of one transistor pair and the NPN of the other transistor pair are able to operate as a distributed silicon controlled rectifier to protect a drive transistor during an ESD event. Optionally, a switching V.sub.DD bus may also be incorporated and a third transistor pair having emitters coupled to the switching V.sub.DD bus may be employed.

    Abstract translation: 具有用于隔离开关噪声的开关接地总线的集成电路的静电放电（ESD）保护电路包括ESD保护总线。 第一晶体管对包括PNP晶体管和NPN晶体管，其中每个晶体管具有连接到信号输入/输出焊盘的发射极。 第二晶体管对具有PNP晶体管和NPN晶体管，其具有连接到开关接地总线的发射极。 对于每个PNP晶体管，基极连接到ESD保护总线，并且集电极连接到“干净”的接地总线。 对于每个NPN晶体管，基极连接到干净的接地总线，并且集电极连接到ESD保护总线。 在这种配置中，一个晶体管对的PNP和另一个晶体管对的NPN能够作为分布式可控硅整流器工作，以在ESD事件期间保护驱动晶体管。 可选地，还可以并入开关VDD总线，并且可以采用具有耦合到开关VDD总线的发射极的第三晶体管对。

    Optical enhancement of integrated circuit photodetectors
    6.
    发明申请
    Optical enhancement of integrated circuit photodetectors 有权
    集成电路光电探测器的光学增强

    公开(公告)号：US20070158696A1

    公开(公告)日：2007-07-12

    申请号：US11716863

    申请日：2007-03-12

    Applicant: Chintamani Palsule ,  John Stanback ,  Thomas Dungan ,  Mark Crook

    Inventor： Chintamani Palsule ,  John Stanback ,  Thomas Dungan ,  Mark Crook

    IPC: H01L27/148

    CPC classification number: H01L27/1462 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14685

    Abstract: A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device integral with a semiconductor substrate, a cover dielectric layer disposed over the light sensitive device, and a lens-formation dielectric layer disposed over the cover dielectric layer. Light is transmittable through the cover dielectric layer; and through the lens-formation dielectric layer. The lens-formation dielectric layer forms an embedded convex microlens. The microlens directs light onto the light sensitive device.

    Abstract translation: 一种半导体集成电路结构及其制造方法。 半导体集成电路结构包括与半导体衬底整体的光敏器件，设置在光敏器件上的覆盖电介质层，以及设置在覆盖电介质层上的透镜形成电介质层。 光通过覆盖电介质层可传输; 并透过透镜形成电介质层。 透镜形成电介质层形成嵌入的凸形微透镜。 微透镜将光引导到光敏设备上。

    Bipolar transistor with nonselective epitaxial base and raised extrinsic base
    7.
    发明申请
    Bipolar transistor with nonselective epitaxial base and raised extrinsic base 审中-公开
    具有非选择性外延基极和增强的外在基极的双极晶体管

    公开(公告)号：US20060006416A1

    公开(公告)日：2006-01-12

    申请号：US10886461

    申请日：2004-07-07

    Applicant: Nathan Perkins ,  Thomas Dungan

    Inventor： Nathan Perkins ,  Thomas Dungan

    IPC: H01L29/739

    CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/732

    Abstract: A method for forming a transistor that includes forming an intrinsic base on a substrate using nonselective epitaxy and forming a raised extrinsic base on the intrinsic base. The nonselective epitaxy used to form the intrinsic base avoids the costly, complex, and defect prone process of selective epitaxy while the raised extrinsic base avoids the high resistance, high noise, low gain, and base contact problems found in prior transistors having thin base regions.

    Abstract translation: 一种用于形成晶体管的方法，其包括使用非选择性外延在衬底上形成本征基极并在本征基底上形成凸起的外部基极。 用于形成本征基极的非选择性外延避免了选择性外延的昂贵的，复杂的和缺陷的过程，而增强的外部基极避免了在具有薄的基极区域的现有晶体管中发现的高电阻，高噪声，低增益和基极接触问题 。

    Monolithic vertical integration of an acoustic resonator and electronic circuitry
    10.
    发明申请
    Monolithic vertical integration of an acoustic resonator and electronic circuitry 失效
    声谐振器和电子电路的单片垂直集成

    公开(公告)号：US20060202779A1

    公开(公告)日：2006-09-14

    申请号：US11079776

    申请日：2005-03-14

    Applicant: R. Fazzio ,  Thomas Dungan

    Inventor： R. Fazzio ,  Thomas Dungan

    IPC: H03H9/54

    CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C2203/0735 ,  H03H9/0557 ,  Y10T29/42

    Abstract: Monolithic devices that include an acoustic resonator vertically integrated with electronic circuitry are described. In one aspect, a monolithic integrated device includes a substrate, electronic circuitry supported by the substrate, an acoustic isolator over the electronic circuitry, and an acoustic resonator on the acoustic isolator. A method of fabricating the monolithic device also is described.

    Abstract translation: 描述了包括与电子电路垂直集成的声谐振器的单片器件。 一方面，单片集成器件包括衬底，由衬底支撑的电子电路，电子电路上的声学隔离器以及声学隔离器上的声学谐振器。 还描述了制造单片装置的方法。

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