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    Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof
    1.
    发明授权
    Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof 有权
    集成电阻器，包括该电阻器的相变存储元件及其制造方法

    公开(公告)号：US06946673B2

    公开(公告)日：2005-09-20

    申请号：US10345129

    申请日：2003-01-14

    申请人： Romina Zonca ,  Maria Santina Marangon ,  Giorgio De Santi

    发明人： Romina Zonca ,  Maria Santina Marangon ,  Giorgio De Santi

    IPC分类号： H01L45/00 ,  H01L47/00 ,  H01L29/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

    摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。

    Process for manufacturing integrated resistor and phase-change memory element including this resistor
    2.
    发明申请
    Process for manufacturing integrated resistor and phase-change memory element including this resistor 审中-公开
    集成电阻器和包括该电阻器的相变存储元件的制造工艺

    公开(公告)号：US20050269667A1

    公开(公告)日：2005-12-08

    申请号：US11201790

    申请日：2005-08-11

    申请人： Romina Zonca ,  Maria Marangon ,  Giorgio De Santi

    发明人： Romina Zonca ,  Maria Marangon ,  Giorgio De Santi

    IPC分类号： H01L45/00 ,  H01L29/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

    摘要： A vertical-current-flow resistive element includes a monolithic region having a first portion and a second portion arranged on top of one another and formed from a single material. The first portion has a first resistivity, and the second portion has a second resistivity, lower than the first resistivity. To this aim, a monolithic region with a uniform resistivity and a height greater than at least one of the other dimensions is first formed; then the resistivity of the first portion is increased by introducing, from the top, species that form a prevalently covalent bond with the conductive material of the monolithic region, so that the concentration of said species becomes higher in the first portion than in the second portion. Preferably, the conductive material is a binary or ternary alloy, chosen from among TiAl, TiSi, TiSi2, Ta, WSi, and the increase in resistivity is obtained by nitridation.

    摘要翻译： 垂直电流阻力元件包括具有第一部分和第二部分的整体区域，第一部分和第二部分彼此顶部布置并由单一材料形成。 第一部分具有第一电阻率，第二部分具有低于第一电阻率的第二电阻率。 为此目的，首先形成具有均匀的电阻率和高于其它尺寸中的至少一个的高度的整体区域; 那么通过从顶部引入与整体区域的导电材料形成普遍共价键的物质来增加第一部分的电阻率，使得所述物质的浓度在第一部分中比在第二部分中更高 。 优选地，导电材料是选自TiAl，TiSi，TiSi 2，Ta，WSi的二元或三元合金，并且通过氮化获得电阻率的增加。

    Small area contact region, high efficiency phase change memory cell and fabrication method thereof
    5.
    发明授权
    Small area contact region, high efficiency phase change memory cell and fabrication method thereof 有权
    小面积接触区域，高效率相变存储单元及其制造方法

    公开(公告)号：US07227171B2

    公开(公告)日：2007-06-05

    申请号：US10313991

    申请日：2002-12-05

    申请人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

    发明人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

    IPC分类号： H01L29/04

    CPC分类号： G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

    摘要： A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

    摘要翻译： 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。

    Phase change memory cell and manufacturing method thereof using minitrenches
    6.
    发明授权
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元及其制造方法

    公开(公告)号：US06891747B2

    公开(公告)日：2005-05-10

    申请号：US10372761

    申请日：2003-02-20

    申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G11C11/00

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    摘要翻译： 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    PHASE CHANGE MEMORY CELL AND MANUFACTURING METHOD THEREOF USING MINITRENCHES
    7.
    发明申请
    PHASE CHANGE MEMORY CELL AND MANUFACTURING METHOD THEREOF USING MINITRENCHES 有权
    相变存储器单元及其使用MINITRENCHES的制造方法

    公开(公告)号：US20110237045A1

    公开(公告)日：2011-09-29

    申请号：US13158291

    申请日：2011-06-10

    申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC分类号： H01L21/20

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    Phase change memory cell and manufacturing method thereof using minitrenches
    8.
    发明授权
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元及其制造方法

    公开(公告)号：US07993957B2

    公开(公告)日：2011-08-09

    申请号：US11045170

    申请日：2005-01-27

    申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC分类号： H01L21/00

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    Manufacturing process of a semiconductor non-volatile memory cell
    9.
    发明授权
    Manufacturing process of a semiconductor non-volatile memory cell 有权
    半导体非易失性存储单元的制造工艺

    公开(公告)号：US07262098B2

    公开(公告)日：2007-08-28

    申请号：US10323615

    申请日：2002-12-18

    申请人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

    发明人： Mauro Alessandri ,  Barbara Crivelli ,  Romina Zonca

    IPC分类号： H01L29/78

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

    摘要翻译： 一种用于制造具有至少一个栅极区域的非易失性存储单元的工艺，所述方法包括以下步骤：将第一介电层沉积到半导体衬底上; 在所述第一介电层上沉积第一半导体层以形成所述存储单元的浮动栅区; 以及限定第一半导体层中的存储单元的浮置栅极区。 该方法还包括在第一导电层上沉积第二电介质层的步骤，第二电介质层具有比10更高的介电常数。还公开了集成在半导体衬底中并具有栅极区的存储单元，该栅极区具有电介质 层形成在第一导电层上并具有高于10的介电常数。