公开(公告)号：US07227171B2

公开(公告)日：2007-06-05

申请号：US10313991

申请日：2002-12-05

申请人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

IPC分类号： H01L29/04

CPC分类号： G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

摘要： A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

摘要翻译： 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。

公开(公告)号：US09876166B2

公开(公告)日：2018-01-23

申请号：US13158291

申请日：2011-06-10

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L45/00 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

公开(公告)号：US20110237045A1

公开(公告)日：2011-09-29

申请号：US13158291

申请日：2011-06-10

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： H01L21/20

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US07993957B2

公开(公告)日：2011-08-09

申请号：US11045170

申请日：2005-01-27

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US06891747B2

公开(公告)日：2005-05-10

申请号：US10372761

申请日：2003-02-20

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G11C11/00

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

摘要翻译： 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US20050152208A1

公开(公告)日：2005-07-14

申请号：US11045170

申请日：2005-01-27

申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G01R31/08

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

公开(公告)号：US06294431B1

公开(公告)日：2001-09-25

申请号：US09547520

申请日：2000-04-12

申请人： Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

发明人： Roberto Bez ,  Caterina Riva ,  Giorgio Servalli

IPC分类号： H01L218247

CPC分类号： H01L27/11521

摘要： A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines. In said step for the definition of the source lines, a process step comprises selectively introducing dopant to form a layer of buried silicon with high concentration of dopant, said layer of buried silicon being formed to such a depth to coincide with the regions of silicon of the underlying field oxide zones, and the introduction of dopant in said active regions of the source lines to superficially contact said layer of buried silicon.

摘要翻译： 一种用于制造具有以矩阵结构的字线和列布置的存储单元的非易失性存储器的过程，其中源极线平行延伸并插入到所述线中，所述源极线由插入到场氧化物区域的有源区形成，所述源极线 过程包括用于定义所述非易失性存储器单元矩阵的所述列的有效区域和所述场氧化物区域的定义的步骤，用于定义所述非易失性存储器单元矩阵的行的后续步骤，以及 以下步骤用于定义所述源线。 在用于定义源极线的所述步骤中，处理步骤包括选择性地引入掺杂剂以形成具有高浓度掺杂剂的掩埋硅层，所述掩埋硅层被形成为与硅的区域重合的深度 底层场氧化物区域，以及在源极线的所述有源区域中引入掺杂剂以表面接触所述掩埋硅层。

公开(公告)号：US20110084247A1

公开(公告)日：2011-04-14

申请号：US12969652

申请日：2010-12-16

申请人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

发明人： Fabio Pellizzer ,  Roberto Bez ,  Paola Zuliani ,  Augusto Benvenuti

IPC分类号： H01L45/00 ,  H01L27/082

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/1022 ,  H01L27/24 ,  H01L29/66272

摘要： A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

摘要翻译： 通过形成公共导电区域，在公共导电区域上的自身有效区域中延伸的多个控制区域，多个硅化物保护带和至少一个控制接触区域来形成多个双极晶体管。 在第二导电区域和控制接触区域上形成硅化物区域。 可以通过在所选择的硅化物保护条的第一侧选择性地注入第一导电类型的掺杂剂区域来形成第二导电区域。 通过在所选择的硅化物保护带的第二侧选择性地注入相反的导电型掺杂剂来形成控制接触区域。

公开(公告)号：US07606056B2

公开(公告)日：2009-10-20

申请号：US11317622

申请日：2005-12-22

申请人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

发明人： Fabio Pellizzer ,  Roberto Bez ,  Maria Santina Marangon ,  Roberta Piva ,  Laura Aina

IPC分类号： G11C5/06

CPC分类号： H01L45/1691 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

摘要翻译： 一种相变存储器阵列的制造方法包括以下步骤：在半导体晶片的阵列区域中形成多个相变存储单元，根据行方向排列成行和列的相变存储单元和列 方向; 在所述半导体晶片的控制区域中形成控制电路; 形成多个第一位线部分，用于相互连接布置在同一列上的相变存储器单元; 形成一级电互连结构; 以及在所述第一级电互连结构之上形成第二级电互连结构。 第一级电互连结构包括布置在第一位线部分上并与第一位线部分接触的第二位线部分，并且在列方向上从第一位线部分突出以将第一位线部分连接到控制电路。

公开(公告)号：US07227765B2

公开(公告)日：2007-06-05

申请号：US10970842

申请日：2004-10-20

申请人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

发明人： Guido De Sandre ,  Roberto Bez ,  Fabio Pellizzer

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

摘要： A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

摘要翻译： 一种用于非易失性内容可寻址存储器的内容可寻址存储器单元，包括用于存储内容数位的非易失性存储元件，用于选择存储单元的选择输入，用于接收搜索数字的搜索输入以及比较电路装置 用于将搜索数字与内容数字进行比较，并用于驱动存储器单元的匹配输出，以便发出内容数字和搜索数字之间的匹配。 非易失性存储元件包括用于以非易失性方式存储相应内容数字的至少一个相变存储器元件。