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    Embedded storage device with integrated data-management functions and storage system incorporating it
    1.
    发明申请
    Embedded storage device with integrated data-management functions and storage system incorporating it 审中-公开
    具有集成数据管理功能的嵌入式存储设备和并入其中的存储系统

    公开(公告)号：US20060053252A1

    公开(公告)日：2006-03-09

    申请号：US11205766

    申请日：2005-08-16

    申请人： Stefano Ghezzi ,  Marco Roveda ,  Stefano Saltutti ,  Giorgio Scarioni

    发明人： Stefano Ghezzi ,  Marco Roveda ,  Stefano Saltutti ,  Giorgio Scarioni

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0661 ,  G06F3/0664 ,  G06F3/0679

    摘要： In a storage system, a system controller is connected to an embedded storage device for supervising writing and reading operations in the embedded storage device. A data manager based upon a microprocessor is integrated in the embedded storage device and provides a high-level abstraction of the physical organization of the embedded storage device through the definition of an own logic map. The data manager is implemented outside the controller. The controller is formed in a first semiconductor material region, the embedded storage device is formed in a second semiconductor material region distinct from the first semiconductor material region, and the data manager is formed in a third semiconductor material region distinct from the first semiconductor material region.

    摘要翻译： 在存储系统中，系统控制器连接到嵌入式存储设备，用于监控嵌入式存储设备中的写入和读取操作。 基于微处理器的数据管理器集成在嵌入式存储设备中，并且通过定义自己的逻辑图来提供嵌入式存储设备的物理组织的高级抽象。 数据管理器在控制器外部实现。 控制器形成在第一半导体材料区域中，嵌入式存储装置形成在与第一半导体材料区域不同的第二半导体材料区域中，数据管理器形成在与第一半导体材料区域不同的第三半导体材料区域中 。

    Memory cell integrated structure with corresponding biasing device
    3.
    发明授权
    Memory cell integrated structure with corresponding biasing device 有权
    存储单元集成结构与相应的偏置装置

    公开(公告)号：US6151251A

    公开(公告)日：2000-11-21

    申请号：US295667

    申请日：1999-04-21

    申请人： Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti ,  Stefano Ghezzi

    发明人： Giovanni Campardo ,  Stefano Zanardi ,  Maurizio Branchetti ,  Stefano Ghezzi

    IPC分类号： G05F3/20 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/115 ,  G05F3/205

    摘要： A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.

    摘要翻译： 一种用于偏置具有与其相关联的衬底偏置端子的存储单元的偏置装置。 偏置装置包括第一子阈值电路块，其适于在器件待机阶段期间通过连接在电源电压基准和存储单元的衬底偏置端之间的恢复晶体管提供适当的电流，并且具有连接到存储器单元的控制端 偏置电路又连接在电源参考电压和地电压基准之间，以有限的电流驱动恢复晶体管。 该装置还包括用于对衬底偏置端子进行快速充电的第二反馈块，其连接在电源电压基准和接地电压基准之间，并且包括具有经由稳定晶体管连接到接地电压基准的控制端的第一偏置晶体管， 连接到输出节点的控制终端，以及连接在电源电压基准和接地电压基准之间的第一调节晶体管的控制端，稳压晶体管和第一调节晶体管为偏置晶体管提供反馈，从而限制 输出节点的电压范围。

    Electronic counter for a non-volatile memory device integrated on a semiconductor
    6.
    发明授权
    Electronic counter for a non-volatile memory device integrated on a semiconductor 有权
    用于集成在半导体上的非易失性存储器件的电子计数器

    公开(公告)号：US06208705B1

    公开(公告)日：2001-03-27

    申请号：US09262500

    申请日：1999-03-04

    申请人： Guido Lomazzi ,  Marco Maccarrone ,  Stefano Ghezzi ,  Donato Ferrario

    发明人： Guido Lomazzi ,  Marco Maccarrone ,  Stefano Ghezzi ,  Donato Ferrario

    IPC分类号： G06M300

    CPC分类号： H03K21/00 ,  H03K23/00

    摘要： An electronic counter for a semconductor-integrated non-volatile memory device includes a single count cell connected with its output to at least one storage element The count cell comprises a summing block of the half-adder type and a master portion of a master/slave flip-flop of which said storage element is a slave portion. Advantageously, the master portion has an output connected to the input side of a number n of slave registers arranged in parallel.

    摘要翻译： 一种用于半导体集成非易失性存储器件的电子计数器，包括与其输出端连接至至少一个存储元件的单个计数单元。该计数单元包括半加法器类型的加法块和主/从器件的主器件 其中所述存储元件是从属部分的触发器。 有利地，主机部分具有连接到平行布置的数个n个从属寄存器的输入侧的输出。

    Positive charge pump
    7.
    发明授权
    Positive charge pump 失效
    正电荷泵

    公开(公告)号：US6075402A

    公开(公告)日：2000-06-13

    申请号：US946727

    申请日：1997-10-08

    申请人： Andrea Ghilardelli ,  Jacopo Mulatti ,  Stefano Ghezzi

    发明人： Andrea Ghilardelli ,  Jacopo Mulatti ,  Stefano Ghezzi

    IPC分类号： H02M3/07 ,  G05F1/10

    CPC分类号： H02M3/073

    摘要： A charge pump comprises a plurality of stages connected in series, an input terminal of the charge pump being connected to a voltage supply and an output terminal of the charge pump providing an output voltage higher than the voltage supply. Each stage comprises unidirectional current flow MOS transistor means connected between a stage input terminal and a stage output terminal allowing current to flow only from said stage input terminal to said stage output terminal, and a first capacitor with one plate connected to said stage output terminal and another plate driven by a respective first digital signal periodically switching between ground and said voltage supply. The unidirectional current flow MOS transistor means of the stages have independent bulk electrodes, and a bias voltage generator circuit is provided for biasing the bulk electrodes of said unidirectional current flow MOS transistor means at respective bulk potentials which become progressively higher going from the stages proximate to said input terminal to the stages proximate to said output terminal of the charge pump.

    摘要翻译： 电荷泵包括串联连接的多个级，电荷泵的输入端连接到电压源，电荷泵的输出端提供高于电压源的输出电压。 每个级包括连接在级输入端和级输出端之间的单向电流MOS晶体管装置，允许电流仅从所述级输入端流向所述级输出端;以及第一电容器，其一板连接到所述级输出端，以及 由相应的第一数字信号驱动的另一个板，周期性地在接地和所述电压源之间切换。 级的单向电流MOS晶体管装置具有独立的体电极，并且提供偏置电压发生器电路，用于以相应的体积电位偏压所述单向电流流量MOS晶体管装置的体电极，其逐渐地从接近于 所述输入端子接近电荷泵的所述输出端子的级。

    Power on reset circuit with auto turn off
    8.
    发明授权
    Power on reset circuit with auto turn off 失效
    上电复位电路，自动关机

    公开(公告)号：US5929674A

    公开(公告)日：1999-07-27

    申请号：US846757

    申请日：1997-04-30

    申请人： Marco Maccarrone ,  Stefano Ghezzi ,  Maurizio Branchetti

    发明人： Marco Maccarrone ,  Stefano Ghezzi ,  Maurizio Branchetti

    IPC分类号： H03K17/22 ,  H03L7/00

    CPC分类号： H03K17/223

    摘要： The present invention relates to an electronic power on reset circuit of the type including a comparator having at least two inputs and one output for receiving a first reference signal from a generator block and a second signal proportional to a supply voltage from a divider block and for producing an output initialization signal. Advantageously the output is connected to a third turn off enablement input of the comparator through the series of an inverter pair. The generator block and the divider block also include respective turn off enablement inputs connected downstream of the inverter pair.

    摘要翻译： 本发明涉及一种电子上电复位电路，其类型包括具有至少两个输入的比较器和一个用于从发生器模块接收第一参考信号的输出端和与分频器模块的电源电压成比例的第二信号， 产生输出初始化信号。 有利地，输出通过一系列逆变器对连接到比较器的第三关断使能输入端。 发电机组和分压器模块还包括连接在逆变器对的下游的相应的关断使能输入。