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    Integrated circuit current regulator
    1.
    发明授权
    Integrated circuit current regulator 失效
    集成电路电流调节器

    公开(公告)号：US07250812B2

    公开(公告)日：2007-07-31

    申请号：US10908289

    申请日：2005-05-05

    申请人： Roland Frech ,  Bernd Garben

    发明人： Roland Frech ,  Bernd Garben

    IPC分类号： G05F1/10

    CPC分类号： G06F1/26

    摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.

    摘要翻译： 集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。 第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制 相应的片上电源旁路。 每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。 旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。 实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

    INTEGRATED CIRCUIT CURRENT REGULATOR
    3.
    发明申请
    INTEGRATED CIRCUIT CURRENT REGULATOR 失效
    集成电路电流调节器

    公开(公告)号：US20050248390A1

    公开(公告)日：2005-11-10

    申请号：US10908289

    申请日：2005-05-05

    申请人： Roland Frech ,  Bernd Garben

    发明人： Roland Frech ,  Bernd Garben

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26

    摘要： An integrated circuit current regulator that compensates for variation in current required based on the switching activity of the integrated circuit. A first embodiment incorporates a voltage controlled on-chip bypass circuit with a scaling unit to divide an input voltage into n fractional voltages and an on-chip voltage monitor to compare a fraction of the on-chip supply voltage with a reference voltage and control a corresponding on-chip power supply bypass. At least one bypass resistor per comparator is switched between the supply voltage and ground potential according to the output signal of the corresponding comparator to dampen power supply noise. The value of the by-pass resistance R increases with decreasing on-chip supply voltage and decreases with increasing supply voltage. A resistance as a function of supply voltage R(Vdd) characteristic is realized to reduce or eliminate mid-frequency power supply noise, caused by on-chip switching activity variations while minimizing additional on-chip power dissipation.

    摘要翻译： 集成电路电流调节器，其基于集成电路的开关活动来补偿所需电流的变化。 第一实施例包括具有缩放单元的电压控制片上旁路电路，以将输入电压分成n个分数电压，并且片上电压监视器将片上电源电压的一部分与参考电压进行比较，并且控制 相应的片上电源旁路。 每个比较器至少有一个旁路电阻根据相应比较器的输出信号在电源电压和地电位之间切换，以抑制电源噪声。 旁路电阻R的值随着片上电源电压的降低而增加，随着电源电压的增加而减小。 实现了作为电源电压R（Vdd）特性的电阻，以减少或消除由片上开关活动变化引起的中频电源噪声，同时最大限度地减少额外的片上功耗。

    Method for delta-noise reduction
    4.
    发明授权
    Method for delta-noise reduction 失效
    减少降噪的方法

    公开(公告)号：US06774836B2

    公开(公告)日：2004-08-10

    申请号：US10462529

    申请日：2003-06-16

    申请人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

    发明人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Andreas Huber ,  Dierk Kaller ,  Erich Klink ,  Thomas-Michael Winkel ,  Wiren Dale Becker

    IPC分类号： H04L1702

    CPC分类号： G05F1/46

    摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.

    摘要翻译： 一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。 为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案 最小化每个活动单位设备当定期运行时的当前需求。 选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动 在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

    Method for reducing a transient thermal mismatch
    6.
    发明授权
    Method for reducing a transient thermal mismatch 失效
    降低瞬态热失配的方法

    公开(公告)号：US5956563A

    公开(公告)日：1999-09-21

    申请号：US765525

    申请日：1997-01-09

    申请人： Erich Klink ,  Dietmar Schmunkamp ,  Helmut Weber ,  Roland Frech ,  Bernd Garben ,  Hubert Harrer

    发明人： Erich Klink ,  Dietmar Schmunkamp ,  Helmut Weber ,  Roland Frech ,  Bernd Garben ,  Hubert Harrer

    IPC分类号： G06F1/20 ,  G06F1/10 ,  H01L21/321 ,  H01L21/60 ,  H01L23/34 ,  H03L7/06 ,  H01L21/00

    CPC分类号： H01L23/34 ,  H01L2924/0002 ,  H01L2924/09701

    摘要： The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.

    摘要翻译： PCT No.PCT / EP95 / 02152 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT Filed June 6，1995 PCT Pub。 公开号WO96 / 39714 PCT 日期：1996年12月12日本发明涉及一种降低彼此机械接触的第一部件和第二部件之间的瞬态热失配的方法。 第一部件的温度由其消耗的能量的量来控制。 根据输入到第一组件的数据模式来控制消耗的能量，这导致组件内的一定数量的门在每个时钟周期内切换。 通过根据要切换的栅极的数量确定期望的能量耗散并且相应地布置输入数据模式，可以减少部件之间的热失配。

    Mesh planes for multilayer module
    7.
    发明授权
    Mesh planes for multilayer module 失效
    多层模块的网格平面

    公开(公告)号：US5812380A

    公开(公告)日：1998-09-22

    申请号：US765526

    申请日：1997-01-09

    申请人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Erich Klink

    发明人： Roland Frech ,  Bernd Garben ,  Hubert Harrer ,  Erich Klink

    IPC分类号： H01L25/00 ,  H01L23/522 ,  H01L23/538 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16

    CPC分类号： H01L23/5383 ,  H01L2224/16225 ,  H01L2924/09701

    摘要： A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.

    摘要翻译： PCT No.PCT / EP95 / 02194 Sec。 371日期1997年1月9日 102（e）日期1997年1月9日PCT提交1995年6月7日PCT公布。 公开号WO96 / 41376 日期1996年12月19日一种用于封装至少一个电子部件50的多层模块。该模块包括多个厚膜层以及允许模块间电容器连接的布线结构45。 制造多层模块使得布线结构在厚膜的最上层和第二最上层之间包括部分网格平面46,47,48和49。 通过最大化相邻网格平面之间的互感，多层模块中的逻辑噪声降低。

    Determining local voltage in an electronic system
    8.
    发明授权
    Determining local voltage in an electronic system 有权
    确定电子系统中的局部电压

    公开(公告)号：US08866504B2

    公开(公告)日：2014-10-21

    申请号：US13280626

    申请日：2011-10-25

    申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

    发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

    IPC分类号： G01R31/3187 ,  G01R31/317

    CPC分类号： G01R31/3187 ,  G01R31/31703

    摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

    摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

    Evaluating high frequency time domain in embedded device probing
    9.
    发明授权
    Evaluating high frequency time domain in embedded device probing 失效
    评估嵌入式设备探测中的高频时域

    公开(公告)号：US08645091B2

    公开(公告)日：2014-02-04

    申请号：US13567462

    申请日：2012-08-06

    申请人： Joseph Curtis Diepenbrock ,  Roland Frech

    发明人： Joseph Curtis Diepenbrock ,  Roland Frech

    IPC分类号： G06F19/00

    CPC分类号： G01R31/2837 ,  G01R1/06766 ,  G01R1/06772

    摘要： A method and associated system for evaluating a high-frequency signal (SNE) at a point of interest on a signal path. The high-frequency signal (SNE) at the point of interest on the signal path is calculated by applying an inverse transfer function (iG) for the signal path to an argument of a remote signal (SFE) measured at a remote pickup point on the signal path, wherein the point of interest and the remote pickup point are two distant points on the signal path, wherein the high-frequency signal (SNE) and the remote signal (SFE) are represented as a respective time domain variable, and wherein said calculating is performed by a time domain evaluation process that operates in test equipment for electrical devices. The calculated high-frequency signal (SNE) is transferred to an output device of the test equipment.

    摘要翻译： 一种用于评估信号路径上的兴趣点处的高频信号（SNE）的方法和相关系统。 通过将信号路径的反向传递函数（iG）应用于在远程信号的远程信号（SFE）的自变量上测量的远程信号（SFE）上的远程接收点处的信号路径上的感兴趣点处的高频信号（SNE） 信号路径，其中所述感兴趣点和所述远程拾取点是所述信号路径上的两个远点，其中所述高频信号（SNE）和所述远程信号（SFE）被表示为相应的时域变量，并且其中所述 通过在电气设备的测试设备中运行的时域评估过程来执行计算。 计算出的高频信号（SNE）被传送到测试设备的输出设备。

    Method and system for quantifying the integrity of an on-chip power supply network
    10.
    发明授权
    Method and system for quantifying the integrity of an on-chip power supply network 失效

    公开(公告)号：US06665843B2

    公开(公告)日：2003-12-16

    申请号：US10053197

    申请日：2002-01-18

    申请人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    发明人： Roland Frech ,  Andreas Huber ,  Erich Klink ,  Jochen Supper

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： A method and system for analyzing the dynamic behavior of an electrical circuit to determine whether a voltage level provided by a power supply network drops below a predetermined voltage level during operation of the electrical circuit is described. In a first step, a design data set representing pertinent technical specifications of an electrical or an integrated circuit are read in order to extract location information and value of switching and non-switching capacitance. Next, the circuit and technology propagation speeds are inputted therein. The length for specifying the size of a portion of a circuit area is determined wherein the electrical circuit is formed. Next, the circuit area is divided into a plurality of partitions of a specified size, and the switching capacitance and the non-switching capacitance are separately summarized for each partition. The voltage level drop is then calculated for each partition. Finally, the calculated voltage level drop is displayed in relation to the respective partition. The present method and system can be advantageously used for an on-chip power supply network evaluation as well as for an early chip development process.