公开(公告)号：US10910337B2

公开(公告)日：2021-02-02

申请号：US16594160

申请日：2019-10-07

Applicant: Renesas Electronics Corporation

Inventor： Noriko Okunishi ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

公开(公告)号：US20140374890A1

公开(公告)日：2014-12-25

申请号：US14304949

申请日：2014-06-15

Applicant: Renesas Electronics Corporation

Inventor： Takanori Yamashita ,  Toshinori Kiyohara

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01F2019/085 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/06164 ,  H01L2224/27013 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48477 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78705 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H04L25/0266 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/4554

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

Abstract translation: 在具有半导体芯片和另一半导体芯片的SOP1中，在芯片之间进行线耦合时，可以通过设置最靠近第二线组的第一线组中的线与线间距离 最靠近第一配线组的第二配线组中的导线大于第一配线组中的任何电线与第二配线组之间的线间距离，从而可以提高SOP1的可靠性。

公开(公告)号：US10515877B2

公开(公告)日：2019-12-24

申请号：US15934310

申请日：2018-03-23

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro Sato ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

公开(公告)号：US10777490B2

公开(公告)日：2020-09-15

申请号：US16684897

申请日：2019-11-15

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro Sato ,  Toshinori Kiyohara

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

公开(公告)号：US20200091046A1

公开(公告)日：2020-03-19

申请号：US16684897

申请日：2019-11-15

Applicant: Renesas Electronics Corporation

Inventor： Yukihiro Sato ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

公开(公告)号：US20170323848A1

公开(公告)日：2017-11-09

申请号：US15662058

申请日：2017-07-27

Applicant: Renesas Electronics Corporation

Inventor： Takanori Yamashita ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/64 ,  H04L25/02 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01F19/08

CPC classification number: H01L23/49575 ,  H01F2019/085 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/06164 ,  H01L2224/27013 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48477 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78705 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H04L25/0266 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/4554

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

公开(公告)号：US09754865B2

公开(公告)日：2017-09-05

申请号：US14304949

申请日：2014-06-15

Applicant: Renesas Electronics Corporation

Inventor： Takanori Yamashita ,  Toshinori Kiyohara

IPC: H01L23/495 ,  H01L23/64 ,  H04L25/02 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01F19/08

CPC classification number: H01L23/49575 ,  H01F2019/085 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/06164 ,  H01L2224/27013 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48477 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78705 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/12041 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19104 ,  H04L25/0266 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/4554

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

公开(公告)号：US09257400B2

公开(公告)日：2016-02-09

申请号：US14487762

申请日：2014-09-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Kenji Nishikawa ,  Masato Kanno ,  Mika Yonezawa ,  Shunichi Kaeriyama ,  Toshinori Kiyohara

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/495 ,  H01L23/522 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract translation: 半导体器件具有芯片安装部分，第一半导体芯片和第二半导体芯片。 第一半导体芯片沿其第一主平面面向芯片安装部分的方向安装在芯片安装部分上。 第二半导体芯片的一部分在其第三主平面面向第一半导体芯片的方向上安装在芯片安装部分上。 元件安装部分具有凹口部分。 第二半导体芯片的一部分与切口部分重叠。 在与切口部重叠的第二半导体芯片的第三主平面的区域中，设置有第二电极焊盘。