公开(公告)号：US20180358393A1

公开(公告)日：2018-12-13

申请号：US15937162

申请日：2018-03-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidenori SATO ,  Tatsuya KUNIKIYO ,  Yotaro GOTO

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/341

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H04N5/341 ,  H04N5/378

Abstract: In a solid-state imaging element having two or more photodiodes stacked in a vertical direction in each of pixels, electrons are prevented from moving between the respective photodiodes of the pixels adjacent to each other. The solid-state imaging element is formed by joining together a back surface of a first semiconductor wafer including one of the photodiodes and a wiring layer and a back surface of a second semiconductor wafer including another of the photodiodes and a wiring layer. By forming a first isolation region extending through a first semiconductor substrate forming the first semiconductor wafer and a second isolation region extending through a second semiconductor substrate forming the second semiconductor wafer, the photodiodes of one of the pixels are isolated from another of the pixels.

公开(公告)号：US20180350861A1

公开(公告)日：2018-12-06

申请号：US15934484

申请日：2018-03-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO ,  Fumitoshi TAKAHASHI

IPC: H01L27/146

CPC classification number: H01L27/14609 ,  H01L27/14623 ,  H01L27/14632

Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.

公开(公告)号：US20180053804A1

公开(公告)日：2018-02-22

申请号：US15802937

申请日：2017-11-03

Applicant: Renesas Electronics Corporation

Inventor： Yosuke TAKEUCHI ,  Tatsuya KUNIKIYO

IPC: H01L27/146 ,  H01L31/11

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14698 ,  H01L31/1105

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n−-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n−-type semiconductor region, and a p−-type semiconductor region formed between the n−-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n−-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p−-type semiconductor region is lower than a net impurity concentration in the p-type well.

公开(公告)号：US20170186804A1

公开(公告)日：2017-06-29

申请号：US15363585

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Yosuke TAKEUCHI ,  Tatsuya KUNIKIYO

IPC: H01L27/146

CPC classification number: H01L27/14645 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14698 ,  H01L31/1105

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes an n−-type semiconductor region formed in a p-type well, an n-type semiconductor region formed closer to a main surface of a semiconductor substrate than the n−-type semiconductor region, and a p−-type semiconductor region formed between the n−-type semiconductor region and the n-type semiconductor region. A net impurity concentration in the n−-type semiconductor region is lower than a net impurity concentration in the n-type semiconductor region. A net impurity concentration in the p−-type semiconductor region is lower than a net impurity concentration in the p-type well.

公开(公告)号：US20150111357A1

公开(公告)日：2015-04-23

申请号：US14586452

申请日：2014-12-30

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。

公开(公告)号：US20180315789A1

公开(公告)日：2018-11-01

申请号：US15898197

申请日：2018-02-15

Applicant: Renesas Electronics Corporation

Inventor： Fumitoshi TAKAHASHI ,  Tatsuya KUNIKIYO ,  Hidenori SATO ,  Yotaro GOTO

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/1469

Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor and a photodiode with a pn junction. In plan view, a reflecting layer is formed over an n-type region which configures the photodiode, through an isolation insulating film. The reflecting layer extends over the gate electrode of the transfer transistor through a cap insulating film. A first layer signal wiring is electrically coupled to both the gate electrode and the reflecting layer through a contact hole made in an interlayer insulating film over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.

公开(公告)号：US20140213030A1

公开(公告)日：2014-07-31

申请号：US14155961

申请日：2014-01-15

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。

公开(公告)号：US20180366508A1

公开(公告)日：2018-12-20

申请号：US15983029

申请日：2018-05-17

Applicant: Renesas Electronics Corporation

Inventor： Yotaro GOTO ,  Tatsuya KUNIKIYO ,  Hidenori SATO

IPC: H01L27/146 ,  H01L23/00

Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.

公开(公告)号：US20170118419A1

公开(公告)日：2017-04-27

申请号：US15399878

申请日：2017-01-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keiichi ITAGAKI ,  Tatsuya KUNIKIYO

IPC: H04N5/341 ,  H01L27/146 ,  H04N5/225

CPC classification number: H04N5/341 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689 ,  H04N5/2254

Abstract: Provided are a semiconductor device capable of detecting a light of each color with high accuracy without using a color filter, particularly enhancing detection accuracy of charges obtained by photoelectric conversion of a long-wavelength light, and manufacturing and control methods thereof. The semiconductor device has a p type semiconductor substrate, and first, second and third pixel regions. These regions each include a p type well region in the p type semiconductor substrate and an n type region configuring a pn junction therewith. The p type well region of the first pixel region is thinner, from the main surface to the lowermost portion, than that of the second and third pixel regions. On the side opposite to the main surface of the p type well region of the first and second pixel regions, a buried p type well region contiguous to the p type well region is further placed.

公开(公告)号：US20160093716A1

公开(公告)日：2016-03-31

申请号：US14877521

申请日：2015-10-07

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66 ,  H01L27/115 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.