公开(公告)号：US20090057809A1

公开(公告)日：2009-03-05

申请号：US12045095

申请日：2008-03-10

申请人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

发明人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

IPC分类号： H01L21/31 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

摘要： By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

摘要翻译： 通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益 由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

公开(公告)号：US07906383B2

公开(公告)日：2011-03-15

申请号：US12045095

申请日：2008-03-10

申请人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

发明人： Ralf Richter ,  Andy Wei ,  Manfred Horstmann ,  Joerg Hohage

IPC分类号： H01L21/8238 ,  H01L21/311 ,  H01L21/70 ,  H01L27/085

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

摘要： By forming a stressed dielectric layer on different transistors and subsequently relaxing a portion thereof, the overall process efficiency in an approach for creating strain in channel regions of transistors by stressed overlayers may be enhanced while nevertheless transistor performance gain may be obtained for each type of transistor, since a highly stressed material positioned above the previously relaxed portion may also efficiently affect the underlying transistor.

摘要翻译： 通过在不同的晶体管上形成应力介电层并随后放松其一部分，可以增强用于通过应力覆盖层在晶体管的沟道区域中产生应变的方法中的整体工艺效率，同时可以为每种类型的晶体管获得晶体管性能增益 由于位于先前松弛部分之上的高应力材料也可有效地影响底层晶体管。

公开(公告)号：US08546274B2

公开(公告)日：2013-10-01

申请号：US12835967

申请日：2010-07-14

申请人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

发明人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

摘要： A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

摘要翻译： 可以以保形方式沉积高应力电介质材料，例如拉伸应力材料，以便遵循由高比例尺度的半导体器件的显着表面形貌引起的任何沉积约束，随后沉积具有增强间隙的缓冲材料， 填充能力。 此后，沉积另外的应力诱导层以形成作用于晶体管元件的双重结构，从而提高整体性能，而不增加产生沉积相关不规则性的可能性。 因此，可以提高高标度的半导体器件的生产率以及性能。

公开(公告)号：US20090166800A1

公开(公告)日：2009-07-02

申请号：US12165756

申请日：2008-07-01

申请人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

发明人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

IPC分类号： H01L21/31 ,  H01L27/08

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7833 ,  H01L29/7843

摘要： By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

摘要翻译： 通过在不同应力的接触蚀刻停止层上形成缓冲材料，随后沉积另外的应力诱导材料，可以实现增强的整体器件性能，其中附加应力诱导层的不期望的影响可能在器件区域中减小， 例如，通过去除附加材料或通过进行松弛植入工艺。 此外，在用于形成接触开口的图案化顺序期间的工艺均匀性可以通过在要形成接触开口的区域部分去除附加的应力诱导层来增强。

公开(公告)号：US20080081480A1

公开(公告)日：2008-04-03

申请号：US11742878

申请日：2007-05-01

申请人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

发明人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。

公开(公告)号：US08759232B2

公开(公告)日：2014-06-24

申请号：US13588460

申请日：2012-08-17

申请人： Joerg Hohage ,  Hartmut Ruelke ,  Ralf Richter

发明人： Joerg Hohage ,  Hartmut Ruelke ,  Ralf Richter

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76832 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.

摘要翻译： 本公开提供了制造技术和半导体器件，其中可以基于涉及沉积介电双层系统的应力机制来增强P沟道晶体管的性能。 与常规策略相反，可以在粘附层在无等离子体的工艺气氛中沉积之前进行另外的预处理，从而能够减小粘合层的厚度和随后的顶层的更高的内应力水平。

公开(公告)号：US08450172B2

公开(公告)日：2013-05-28

申请号：US12823660

申请日：2010-06-25

申请人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

发明人： Ralf Richter ,  Hartmut Ruelke ,  Joerg Hohage

IPC分类号： H01L21/8238 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

摘要： In sophisticated semiconductor devices, non-insulating materials with extremely high internal stress level may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors, wherein the non-insulating material may be appropriately “encapsulated” by dielectric material. Consequently, a desired high strain level may be obtained on the basis of a reduced layer thickness, while still providing the insulating characteristics required in the contact level.

摘要翻译： 在复杂的半导体器件中，可以在接触电平中使用具有非常高的内部应力水平的非绝缘材料，以便增强诸如场效应晶体管的电路元件的性能，其中非绝缘材料可以被适当地“封装” 介电材料。 因此，可以基于减小的层厚度获得期望的高应变水平，同时仍然提供接触水平所需的绝缘特性。

公开(公告)号：US20090001453A1

公开(公告)日：2009-01-01

申请号：US12017793

申请日：2008-01-22

申请人： Ralf Richter ,  Joerg Hohage ,  Michael Finken ,  Jana Schlott

发明人： Ralf Richter ,  Joerg Hohage ,  Michael Finken ,  Jana Schlott

IPC分类号： H01L29/78 ,  H01L21/322

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.

摘要翻译： 形成半导体结构的方法包括提供包括至少一个晶体管元件的半导体衬底。 在晶体管元件上形成蚀刻停止层。 在蚀刻停止层上形成受应力的第一介电层。 在第一电介质层上形成适于将水分侵入第一电介质层的保护层。 形成至少一个到晶体管元件的电连接。 在形成至少一个电连接完成之后，至少一部分保护层保留在第一介电层上。

公开(公告)号：US07938973B2

公开(公告)日：2011-05-10

申请号：US11733350

申请日：2007-04-10

申请人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

发明人： Ralf Richter ,  Joerg Hohage ,  Martin Mazur

IPC分类号： H01B13/00

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76802

摘要： By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.

摘要翻译： 通过在溅射蚀刻期间结合在处理室的室壁上表现出高粘附性的材料，可以显着地减少基于ARC层的图案化顺序中的缺陷率，因为粘合材料可以在溅射预清洗期间可靠地暴露 处理。 相应的粘合层可以定位在ARC层堆叠内，以便至少部分地可靠地消耗，同时仍然提供所需的光学特性。 因此，可以实现低缺陷率与高工艺效率的组合。

公开(公告)号：US07550396B2

公开(公告)日：2009-06-23

申请号：US11742878

申请日：2007-05-01

申请人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

发明人： Kai Frohberg ,  Volker Grimm ,  Sven Mueller ,  Matthias Lehr ,  Ralf Richter ,  Jochen Klais ,  Martin Mazur ,  Heike Salz ,  Joerg Hohage ,  Matthias Schaller

IPC分类号： H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

摘要： By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

摘要翻译： 通过进行等离子体处理以有效地密封包含氮化硅的应力介电层的表面，可以实现在接触开口的图案化期间提高的性能，因为在所选择的图形化应力层的选择性图案化期间可以显着降低氮诱导的抗蚀剂中毒 不同类型的内在应力。