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    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS
    1.
    发明申请
    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS 有权
    包含耐压材料双层结构的半导体器件中的中间层介电材料

    公开(公告)号：US20090166800A1

    公开(公告)日：2009-07-02

    申请号：US12165756

    申请日：2008-07-01

    申请人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    发明人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    IPC分类号： H01L21/31 ,  H01L27/08

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7833 ,  H01L29/7843

    摘要： By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

    摘要翻译： 通过在不同应力的接触蚀刻停止层上形成缓冲材料，随后沉积另外的应力诱导材料，可以实现增强的整体器件性能，其中附加应力诱导层的不期望的影响可能在器件区域中减小， 例如，通过去除附加材料或通过进行松弛植入工艺。 此外，在用于形成接触开口的图案化顺序期间的工艺均匀性可以通过在要形成接触开口的区域部分去除附加的应力诱导层来增强。

    Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials
    2.
    发明授权
    Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials 有权
    包含应力材料的双重结构的半导体器件中的层间电介质材料

    公开(公告)号：US08034726B2

    公开(公告)日：2011-10-11

    申请号：US12165756

    申请日：2008-07-01

    申请人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    发明人： Ralf Richter ,  Michael Finken ,  Joerg Hohage ,  Heike Salz

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7833 ,  H01L29/7843

    摘要： By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.

    摘要翻译： 通过在不同应力的接触蚀刻停止层上形成缓冲材料，随后沉积另外的应力诱导材料，可以实现增强的整体器件性能，其中附加应力诱导层的不期望的影响可能在器件区域中减小， 例如，通过去除附加材料或通过进行松弛植入工艺。 此外，在用于形成接触开口的图案化顺序期间的工艺均匀性可以通过在要形成接触开口的区域部分去除附加的应力诱导层来增强。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION
    5.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING A FIELD EFFECT TRANSISTOR HAVING A STRESSED CHANNEL REGION 有权
    形成具有应力通道区域的场效应晶体管的半导体结构的方法

    公开(公告)号：US20090001453A1

    公开(公告)日：2009-01-01

    申请号：US12017793

    申请日：2008-01-22

    申请人： Ralf Richter ,  Joerg Hohage ,  Michael Finken ,  Jana Schlott

    发明人： Ralf Richter ,  Joerg Hohage ,  Michael Finken ,  Jana Schlott

    IPC分类号： H01L29/78 ,  H01L21/322

    CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7843

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising at least one transistor element. An etch stop layer is formed over the transistor element. A stressed first dielectric layer is formed over the etch stop layer. A protective layer adapted to reduce an intrusion of moisture into the first dielectric layer is formed over the first dielectric layer. At least one electrical connection to the transistor element is formed. At least a portion of the protective layer remains over the first dielectric layer after completion of the formation of the at least one electrical connection.

    摘要翻译： 形成半导体结构的方法包括提供包括至少一个晶体管元件的半导体衬底。 在晶体管元件上形成蚀刻停止层。 在蚀刻停止层上形成受应力的第一介电层。 在第一电介质层上形成适于将水分侵入第一电介质层的保护层。 形成至少一个到晶体管元件的电连接。 在形成至少一个电连接完成之后，至少一部分保护层保留在第一介电层上。

    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material
    6.
    发明授权
    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material 有权
    在包括具有中间缓冲材料的应力层的半导体器件中的层间电介质材料

    公开(公告)号：US08546274B2

    公开(公告)日：2013-10-01

    申请号：US12835967

    申请日：2010-07-14

    申请人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    发明人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

    摘要： A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

    摘要翻译： 可以以保形方式沉积高应力电介质材料，例如拉伸应力材料，以便遵循由高比例尺度的半导体器件的显着表面形貌引起的任何沉积约束，随后沉积具有增强间隙的缓冲材料， 填充能力。 此后，沉积另外的应力诱导层以形成作用于晶体管元件的双重结构，从而提高整体性能，而不增加产生沉积相关不规则性的可能性。 因此，可以提高高标度的半导体器件的生产率以及性能。

    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL
    8.
    发明申请
    INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL 有权
    在具有中间缓冲材料的包含层的半导体器件中的中间层介电材料

    公开(公告)号：US20100276790A1

    公开(公告)日：2010-11-04

    申请号：US12835967

    申请日：2010-07-14

    申请人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    发明人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    IPC分类号： H01L29/51 ,  H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

    摘要： A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

    摘要翻译： 可以以保形方式沉积高应力电介质材料，例如拉伸应力材料，以便遵循由高比例尺度的半导体器件的显着表面形貌引起的任何沉积约束，随后沉积具有增强间隙的缓冲材料， 填充能力。 此后，沉积另外的应力诱导层以形成作用于晶体管元件的双重结构，从而提高整体性能，而不增加产生沉积相关不规则性的可能性。 因此，可以提高高标度的半导体器件的生产率以及性能。

    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material
    10.
    发明授权
    Interlayer dielectric material in a semiconductor device comprising stressed layers with an intermediate buffer material 失效
    在包括具有中间缓冲材料的应力层的半导体器件中的层间电介质材料

    公开(公告)号：US07875561B2

    公开(公告)日：2011-01-25

    申请号：US12166458

    申请日：2008-07-02

    申请人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    发明人： Joerg Hohage ,  Michael Finken ,  Ralf Richter

    IPC分类号： H01L21/31

    CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

    摘要： A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

    摘要翻译： 可以以保形方式沉积高应力电介质材料，例如拉伸应力材料，以便遵循由高比例尺度的半导体器件的显着表面形貌引起的任何沉积约束，随后沉积具有增强间隙的缓冲材料， 填充能力。 此后，沉积另外的应力诱导层以形成作用于晶体管元件的双重结构，从而提高整体性能，而不增加产生沉积相关不规则性的可能性。 因此，可以提高高标度的半导体器件的生产率以及性能。