Invention Grant
US08034726B2 Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials 有权
包含应力材料的双重结构的半导体器件中的层间电介质材料

Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials
Abstract:
By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.
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