知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

98 条记录 (耗时 0.023 秒)

    Circuit configuration and a method for the testing of storage cells
    3.
    发明授权
    Circuit configuration and a method for the testing of storage cells 失效
    电路配置和存储单元测试方法

    公开(公告)号：US4896322A

    公开(公告)日：1990-01-23

    申请号：US168676

    申请日：1988-03-16

    申请人： Rainer Kraus ,  Oskar Kowarik ,  Kurt Hoffmann ,  Manfred Paul

    发明人： Rainer Kraus ,  Oskar Kowarik ,  Kurt Hoffmann ,  Manfred Paul

    IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38

    CPC分类号： G11C29/38 ,  G11C29/36

    摘要： In a circuit configuration and a method for testing storage cells, all of the bit lines lead to one pair of fault lines which is first precharged with mutually-complementary logic levels. All of the storage cells of a word line are always read-out in parallel relative to one another. In the event of "no fault" the pair of fault lines retains its logic states, whereas in the case of a fault one of the fault lines changes its logic state through switching transistors. This is recognized and analyzed by a comparator circuit in the form of an XOR-circuit or an XNOR-circuit.

    摘要翻译： 在用于测试存储单元的电路配置和方法中，所有位线都导致一对故障线，其首先被预充电互补的逻辑电平。 字线的所有存储单元总是相对于彼此并行读出。 在“无故障”的情况下，该对故障线保持其逻辑状态，而在故障的情况下，故障线之一通过开关晶体管改变其逻辑状态。 这是由XOR电路或XNOR电路形式的比较器电路识别和分析的。

    Gate circuit having MOS transistors
    4.
    发明授权
    Gate circuit having MOS transistors 失效
    具有MOS晶体管的栅极电路

    公开(公告)号：US5030861A

    公开(公告)日：1991-07-09

    申请号：US445687

    申请日：1989-11-16

    申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

    发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus

    IPC分类号： H03K17/693 ,  G11C29/34 ,  G11C29/36 ,  G11C29/38 ,  H03K19/096 ,  H03K19/173

    CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C29/36 ,  H03K19/1736

    摘要： A circuit gives each of the input signals at its inputs to a common circuit previously charged to a supply voltage through transfer transistors. When the logical condition is satisfied the common circuit remains charged; otherwise the charge changes. This is detected by a discriminator circuit and the result is indicated at the circuit output. The circuit may be of AND-, OR-, NAND- and NOR design.

    摘要翻译： PCT No.PCT / DE88 / 00158 Sec。 371日期：一九八九年十一月十六日 102（e）日期1989年11月16日PCT提交1988年3月15日PCT Pub。 出版物WO88 / 07292 日期1988年9月22日。电路将其输入端的每个输入信号提供给预先通过传输晶体管充电到电源电压的公共电路。 当满足逻辑条件时，公共电路保持充电; 否则收费变动。 这由鉴频器电路检测，结果在电路输出端指示。 该电路可以是AND-，OR-，NAND-和NOR设计。

    Integrated semiconductor memory
    5.
    再颁专利
    Integrated semiconductor memory 失效
    集成半导体存储器

    公开(公告)号：USRE36061E

    公开(公告)日：1999-01-26

    申请号：US542360

    申请日：1995-10-12

    申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

    发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans Dieter Oberle

    IPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C29/18 ,  G11C29/30 ,  G11C29/00

    CPC分类号： G11C29/30 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/18

    摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

    摘要翻译： 集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。 内部加权电路各自分配给内部位线对中的相应一个。 外部一对位线通常被分配给内部位线。 分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。 位线解码器触发分离晶体管对。 提供外部加权电路。 鉴别器装置和预充电装置连接到外部位线对。 每对内部位线的内部位线彼此分开触发。 每对内部位线的内部位线彼此分开连接到外部位线对。

    Integrated semiconductor memory of the dram type and method for testing the same
    6.
    发明授权
    Integrated semiconductor memory of the dram type and method for testing the same 失效
    集成半导体存储器的类型和测试方法

    公开(公告)号：US5184326A

    公开(公告)日：1993-02-02

    申请号：US494122

    申请日：1990-03-15

    申请人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

    发明人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

    IPC分类号： G11C11/401 ,  G11C11/4094 ,  G11C11/4099 ,  G11C29/00 ,  G11C29/12 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： G11C11/4099 ,  G11C11/4094 ,  G11C29/50 ,  G06F2201/81 ,  G11C11/401

    摘要： An integrated semiconductor memory of the DRAM type includes word lines and bit line pairs. Memory cells in a matrix are connected to the word lines and the bit lines. One evaluator circuit per bit line pair is connected to the bit lines. Each of the bit line pairs is divided into one bit line and one reference bit line during operation. A control line is provided. At least one coupling capacitor is provided for each of the bit lines and each of the reference bit lines having a first lead connected to the bit line pair and a second lead connected to the control line. A method for testing an integrated semiconductor memory of the DRAM type includes reading data stored in memory cells out of the memory cells, precharging bit line pairs to a precharge level before reading out, and feeding an additional potential to each bit line pair after precharging.

    摘要翻译： DRAM类型的集成半导体存储器包括字线和位线对。 矩阵中的存储单元连接到字线和位线。 每个位线对的一个评估器电路连接到位线。 每个位线对在操作期间被分成一个位线和一个参考位线。 提供控制线。 为每个位线提供至少一个耦合电容器，并且每个参考位线具有连接到位线对的第一引线和连接到控制线的第二引线。 用于测试DRAM类型的集成半导体存储器的方法包括从存储器单元中存储的存储单元中读取数据，在读出之前将位线对预充电到预充电电平，以及在预充电之后向每个位线对馈送附加电位。

    Integrated semiconductor circuit
    8.
    发明授权
    Integrated semiconductor circuit 失效
    集成半导体电路

    公开(公告)号：US5276643A

    公开(公告)日：1994-01-04

    申请号：US799907

    申请日：1991-11-26

    申请人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

    发明人： Kurt Hoffmann ,  Rainer Kraus ,  Oskar Kowarik

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C7/06

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： An integrated semiconductor circuit includes word lines and bit lines. A memory region has at least one memory cell field with memory cells addressable through the word lines and the bit lines, and a number of evaluator circuits corresponding to the number of the bit lines. Each of the evaluator circuits is connected with one of the bit lines and divides the one bit line into two at least approximately identical bit line halves. Logic units of a block perform digital processing of data read-out of the memory region through the bit lines and evaluated. Each of the logic units is connected to the two bit line halves of one of the bit lines. Various operating modes of the block of logic units are selected with mode select signals.

    摘要翻译： 集成半导体电路包括字线和位线。 存储器区域具有至少一个具有可通过字线和位线寻址的存储器单元的存储单元区域，以及与位线数量对应的多个求值器电路。 每个评估器电路与一个位线连接，并将一个位线分成两个至少近似相同的位线半部。 块的逻辑单元通过位线执行对存储器区域的数据读出的数字处理并进行评估。 每个逻辑单元连接到其中一个位线的两个位线半部。 通过模式选择信号选择逻辑单元块的各种操作模式。

    Integrated semiconductor memory
    9.
    发明授权
    Integrated semiconductor memory 失效
    集成半导体存储器

    公开(公告)号：US5253209A

    公开(公告)日：1993-10-12

    申请号：US736468

    申请日：1991-07-26

    申请人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans D. Oberle

    发明人： Kurt Hoffmann ,  Oskar Kowarik ,  Rainer Kraus ,  Bernhard Lustig ,  Hans D. Oberle

    IPC分类号： G11C11/401 ,  G01R31/28 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/18 ,  G11C29/34

    CPC分类号： G11C29/18 ,  G11C11/4094 ,  G11C11/4096

    摘要： An integrated semiconductor memory includes a memory cell field having memory cells disposed in matrix form, word lines and internal bit lines forming pairs of internal bit lines for triggering the memory cells. Internal weighting circuits are each assigned to a respective one of the internal bit line pairs. An external pair of bit lines is commonly assigned to the internal bit lines. Pairs of separation transistors are each assigned to a respective one of the internal bit line pairs for electrical separation of the respective internal bit line pair from the external pair of bit lines. A bit line decoder triggers the pairs of separation transistors. An external weighting circuit is provided. A discriminator device and a precharging device are connected to the external bit line pair. The internal bit lines of each pair of internal bit lines are triggered separately from one another. The internal bit lines of each pair of internal bit lines are connected to the external bit line pair separately from one another.

    摘要翻译： 集成半导体存储器包括具有以矩阵形式设置的存储单元的存储单元区，字线和内部位线，形成用于触发存储单元的内部位线对。 内部加权电路各自分配给内部位线对中的相应一个。 外部一对位线通常被分配给内部位线。 分离晶体管对分别被分配给内部位线对中的相应一个，用于将各个内部位线对与外部位线对电气分离。 位线解码器触发分离晶体管对。 提供外部加权电路。 鉴别器装置和预充电装置连接到外部位线对。 每对内部位线的内部位线彼此分开触发。 每对内部位线的内部位线彼此分开连接到外部位线对。