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    Systems and Methods for Approximating Log Likelihood Ratios in a Communication System
    1.
    发明申请
    Systems and Methods for Approximating Log Likelihood Ratios in a Communication System 失效
    在通信系统中近似对数似然比的系统和方法

    公开(公告)号：US20090245433A1

    公开(公告)日：2009-10-01

    申请号：US12406868

    申请日：2009-03-18

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    IPC分类号： H04L27/06

    CPC分类号： H04L25/067 ,  H04L1/0052

    摘要： Systems and methods for computing log likelihood ratios in a communication system are described. A demodulated symbol may be received. A set of scalars may be determined based on a modulation order, a signal-to-noise ratio for the symbol, and a bit of the symbol. At least one log likelihood ratio for the bit may be approximated using a piecewise linear process based on the scalars and the symbol.

    摘要翻译： 描述用于计算通信系统中的对数似然比的系统和方法。 可以接收解调的符号。 可以基于调制阶数，符号的信噪比和符号的位来确定一组标量。 可以使用基于标量和符号的分段线性处理来近似该比特的至少一个对数似然比。

    Systems and methods for approximating log likelihood ratios in a communication system
    2.
    发明授权
    Systems and methods for approximating log likelihood ratios in a communication system 失效
    用于在通信系统中近似对数似然比的系统和方法

    公开(公告)号：US08761316B2

    公开(公告)日：2014-06-24

    申请号：US12406868

    申请日：2009-03-18

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Sameer Vermani

    IPC分类号： H04L27/06

    CPC分类号： H04L25/067 ,  H04L1/0052

    摘要： Systems and methods for computing log likelihood ratios in a communication system are described. A demodulated symbol may be received. A set of scalars may be determined based on a modulation order, a signal-to-noise ratio for the symbol, and a bit of the symbol. At least one log likelihood ratio for the bit may be approximated using a piecewise linear process based on the scalars and the symbol.

    摘要翻译： 描述用于计算通信系统中的对数似然比的系统和方法。 可以接收解调的符号。 可以基于调制阶数，符号的信噪比和符号的位来确定一组标量。 可以使用基于标量和符号的分段线性处理来近似该比特的至少一个对数似然比。

    Multiple stage fourier transform apparatus, processes, and articles of manufacture
    3.
    发明授权
    Multiple stage fourier transform apparatus, processes, and articles of manufacture 有权
    多级傅里叶变换装置，工艺和制品

    公开(公告)号：US08218426B2

    公开(公告)日：2012-07-10

    申请号：US12408363

    申请日：2009-03-20

    申请人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    发明人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    IPC分类号： H04J11/00

    CPC分类号： H04L27/265 ,  G06F17/142 ,  H04L27/263

    摘要： In embodiments, a fast Fourier transform (FFT) engine includes a series of stages, each stage containing a butterfly and a data normalization device configured to scale output of the stage's butterfly. The scaling factors are adjusted, for example, periodically or on as-needed basis, so that the dynamic range of the butterflies and the buffers is increased for a given bit-width, or the bit-width of these devices is decreased for the same dynamic range. Additionally, bit-width of other buffer(s) is decreased because of the scaling of the data.

    摘要翻译： 在实施例中，快速傅里叶变换（FFT）引擎包括一系列级，每级包含蝴蝶和配置成缩放舞台蝴蝶的输出的数据归一化装置。 比例因子例如可以周期性地或根据需要进行调整，使得蝴蝶和缓冲器的动态范围在给定位宽度上增加，或者这些装置的位宽减小 动态范围。 此外，由于数据的缩放，其他缓冲区的位宽被减小。

    MULTIPLE STAGE FOURIER TRANSFORM APPARATUS, PROCESSES, AND ARTICLES OF MANUFACTURE
    4.
    发明申请
    MULTIPLE STAGE FOURIER TRANSFORM APPARATUS, PROCESSES, AND ARTICLES OF MANUFACTURE 有权
    多级变形装置，工艺和制造文章

    公开(公告)号：US20090268603A1

    公开(公告)日：2009-10-29

    申请号：US12408363

    申请日：2009-03-20

    申请人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    发明人： Hemanth Sampath ,  Kaushik Ghosh ,  Raghu N. Challa ,  Sameer Vermani

    IPC分类号： H04J11/00

    CPC分类号： H04L27/265 ,  G06F17/142 ,  H04L27/263

    摘要： In embodiments, a fast Fourier transform (FFT) engine includes a series of stages, each stage containing a butterfly and a data normalization device configured to scale output of the stage's butterfly. The scaling factors are adjusted, for example, periodically or on as-needed basis, so that the dynamic range of the butterflies and the buffers is increased for a given bit-width, or the bit-width of these devices is decreased for the same dynamic range. Additionally, bit-width of other buffer(s) is decreased because of the scaling of the data.

    摘要翻译： 在实施例中，快速傅里叶变换（FFT）引擎包括一系列级，每级包含蝴蝶和配置成缩放舞台蝴蝶的输出的数据归一化装置。 比例因子例如可以周期性地或根据需要进行调整，使得蝴蝶和缓冲器的动态范围在给定位宽度上增加，或者这些装置的位宽减小 动态范围。 此外，由于数据的缩放，其他缓冲区的位宽被减小。

    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS
    6.
    发明申请
    ARCHITECTURE TO HANDLE CONCURRENT MULTIPLE CHANNELS 有权
    构建多个通道的通道

    公开(公告)号：US20090245435A1

    公开(公告)日：2009-10-01

    申请号：US12413069

    申请日：2009-03-27

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Ali RostamPisheh

    IPC分类号： H04L27/06

    CPC分类号： H04L1/0045 ,  H03M13/2957 ,  H03M13/6566 ,  H04L5/0007 ,  H04L27/2647

    摘要： An apparatus and method for enhanced downlink processing of received channels in a mobile communications system is described, containing a buffer for control data and traffic data, a demapper engine with at least two independently operating demappers for demapping the control and traffic data, a log-likelihood-ratio (LLR) buffer for supporting memory segments accessible by the demapper engine, a decoder engine containing decoders, each of the decoders operating on data from selected memory segment(s) of the LLR buffer, and an arbitrator providing control of at least one of the demapper engine, LLR buffer, and decoder engine. At least one of the decoders is suited for decoding control data and another one of the decoders is suited for decoding traffic data. By partitioning the decoding as such, an increase in downlink throughput can be obtained.

    摘要翻译： 描述了一种用于在移动通信系统中增强接收信道的下行链路处理的装置和方法，其包括用于控制数据和业务数据的缓冲器，具有至少两个独立操作的解映射器的解映射器引擎，用于对所述控制和业务数据进行解映射， 用于支持由解映射器引擎可访问的存储器段的似然比（LLR）缓冲器，包含解码器的解码器引擎，每个解码器对来自所选择的LLR缓冲器的所选存储器段的数据进行操作，以及至少提供至少控制的仲裁器 一个解映射引擎，LLR缓冲区和解码引擎。 解码器中的至少一个适合于解码控制数据，并且解码器中的另一个适合于解码业务数据。 通过分解解码，可以获得下行链路吞吐量的增加。

    Buffered demod and demap functions
    8.
    发明授权
    Buffered demod and demap functions 失效
    缓冲解调和解映射功能

    公开(公告)号：US08520500B2

    公开(公告)日：2013-08-27

    申请号：US12407482

    申请日：2009-03-19

    申请人： Jeremy H. Lin ,  Arunava Chaudhuri ,  Raghu N. Challa ,  Hemanth Sampath

    发明人： Jeremy H. Lin ,  Arunava Chaudhuri ,  Raghu N. Challa ,  Hemanth Sampath

    IPC分类号： H04J11/00

    CPC分类号： H04L25/0202 ,  H04L5/0007 ,  H04L5/0023 ,  H04L27/265

    摘要： An apparatus operable in a wireless communication system, the apparatus may include an FFT symbol buffer and a demapping device. The FFT symbol buffer can feed FFT symbol data derived from received communication signals to a channel estimation device and a shared buffer. The channel estimation device can also provide intermediate data to the shared buffer. The intermediate data may be in tile form and can be derived from the FFT symbol data. Further, the intermediate data can be stored in the shared buffer. The demapping device can extract the intermediate data from the shared buffer in various forms including sub-packet form.

    摘要翻译： 一种在无线通信系统中可操作的装置，该装置可以包括FFT符号缓冲器和解映射装置。 FFT符号缓冲器可以将从接收到的通信信号导出的FFT符号数据馈送到信道估计装置和共享缓冲器。 信道估计装置还可以向共享缓冲器提供中间数据。 中间数据可以是瓦片形式，并且可以从FFT符号数据导出。 此外，中间数据可以存储在共享缓冲器中。 解映射设备可以以包括子包形式的各种形式从共享缓冲器提取中间数据。

    HARDWARE ENGINE TO DEMOD SIMO, MIMO, AND SDMA SIGNALS
    9.
    发明申请
    HARDWARE ENGINE TO DEMOD SIMO, MIMO, AND SDMA SIGNALS 有权
    硬件引擎解析SIMO，MIMO和SDMA信号

    公开(公告)号：US20090304116A1

    公开(公告)日：2009-12-10

    申请号：US12408603

    申请日：2009-03-20

    申请人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

    发明人： Raghu N. Challa ,  Hemanth Sampath ,  Gwendolyn D. Barriac

    IPC分类号： H04L27/06

    CPC分类号： H04L25/03019 ,  H04L2025/03426 ,  H04L2025/03726

    摘要： An apparatus including a configurable demodulation architecture which includes a control module and a demodulation engine. The control module includes a set of one or more control fields. The demodulation engine includes a spatial whitening module, a Minimum Mean Square Estimation (MMSE) module, at least a first Maximal Ratio Combining (MRC) module, and at least one multiplexer. Further, the multiplexer is coupled to the instruction module and controlled based on the control fields to select at least one of the MMSE module or MRC module.

    摘要翻译： 一种包括可配置解调架构的装置，其包括控制模块和解调引擎。 控制模块包括一组一个或多个控制域。 解调引擎包括空间白化模块，最小均方估计（MMSE）模块，至少第一最大比组合（MRC）模块和至少一个多路复用器。 此外，多路复用器耦合到指令模块并且基于控制字段来控制，以选择MMSE模块或MRC模块中的至少一个。